For the "classic" (non-Ruby) m5 memory system, the coherence protocol is pretty tightly integrated with the cache model. I don't know that you can just "disable" it.
You certainly can set different block sizes on different caches (as I think you already tried)... if you really want to pursue this (as opposed to building a sectored L2 cache) then one approach is just to go back to that and see what is breaking. Steve On Mon, Jul 12, 2010 at 9:23 PM, Wang, Weixun <wew...@cise.ufl.edu> wrote: > Hi m5-dev list, > > My understanding of the cache subsystem in M5 is that all caches (L1s in all > cores and L2 in a CMP system) must have the same line size. I understand > that it is more efficient, especially for the coherence protocol. However, I > think it is reasonable for different caches to have different line sizes. I > assume there is no data sharing between workloads for now hence there is no > cache coherence issue (although I think a little bit redesign of the > coherence protocol would make it work). > > I'm interested in modifying M5 to support different line sizes in L1s and > the shared L2 (while L2's line size is always larger than all L1's). Would > anybody give me any suggestion? > > 1) I think modifying the addressing and cache line filling during a L1 miss > is all I have to do, right? Any advice on where I should be looking at? > > 2) For not messing up with coherence protocol, I may need to disable it. Any > advice on where I should be looking at (like, stop each core from snooping > the bus)? Will there be any side-effect if I do this? > > Thanks. > > -- > Best Regards, > > Wang, Weixun > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
