Hi. I've done a little work enabling X86_FS with the timing CPU, but there was a problem where a pointer to a packet was corrupted somehow (if I remember correctly) and it died not very far in. As far as I know that problem was never fixed, and it's quite likely you'll run into silly issues I didn't since I couldn't get all that far. I haven't looked at the Timing CPU's code again yet, but I have to imagine in other ISAs other reads/writes have NO_ACCESS set and don't get held up by the TLB. There may be some mechanism in place to handle this case already that isn't being triggered or is being circumvented somehow. I'll look at it when I get a chance and get back to you. What kernel/configuration script/command line are you using?
Gabe Joel Hestness wrote: > Hi, > I am currently experimenting with the timing CPU in X86_FS, and I > have encountered an assertion failure while booting Linux (using Linux > boot as a test): > m5.debug: build/X86_FS/cpu/simple/timing.cc:900: void > TimingSimpleCPU::completeDataAccess(Packet*): Assertion `_status == > DcacheWaitResponse || _status == DTBWaitResponse' failed. > I have attached a stack trace (note that completeDataAccess is > called twice in the trace). The current macro-instruction is a POP_M, > and the current uop is the Cda. > In timing mode since the Cda doesn't access memory > (the Request::NO_ACCESS flag is set by Cda), it doesn't wait on a > memory access or TLB, so the status of the CPU before the assertion is > _status = Running. I've tried adding "|| _status == Running" to the > conditional in the assertion, and the simulation gets past that point, > but crashes later. I'm not sure if this is a sound fix, or if there > is a better way to handle this. > While browsing the code, I noticed that further up in the call > stack, TimingSimpleCPU::write is called, and when executing this same > test using the atomic CPU, AtomicSimpleCPU::write is called. In the > AtomicSimpleCPU::write code, there is a special case test for > when the Request::NO_ACCESS flag is set. I wonder if the same should > occur in TimingSimpleCPU::write? > Thanks, > Joel > > -- > Joel Hestness > PhD Student, Computer Architecture > Dept. of Computer Science, University of Texas - Austin > http://www.cs.utexas.edu/~hestness > <http://www.cs.utexas.edu/%7Ehestness> > ------------------------------------------------------------------------ > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
