Hey, thanks for that update Gabe! That DPRINTF code was bothering me for awhile and I never got to it...
On Fri, Aug 13, 2010 at 9:32 AM, Gabe Black <[email protected]> wrote: > changeset 28f052c55332 in /z/repo/m5 > details: http://repo.m5sim.org/m5?cmd=changeset;node=28f052c55332 > description: > InOrder: Clean up some DPRINTFs that print data sent to/from the > cache. > > diffstat: > > src/cpu/inorder/resources/cache_unit.cc | 58 > +++++++++++++------------------- > 1 files changed, 23 insertions(+), 35 deletions(-) > > diffs (103 lines): > > diff -r 917208416d2a -r 28f052c55332 > src/cpu/inorder/resources/cache_unit.cc > --- a/src/cpu/inorder/resources/cache_unit.cc Fri Aug 13 06:10:45 2010 > -0700 > +++ b/src/cpu/inorder/resources/cache_unit.cc Fri Aug 13 06:16:00 2010 > -0700 > @@ -47,6 +47,16 @@ > using namespace TheISA; > using namespace ThePipeline; > > +static std::string > +printMemData(uint8_t *data, unsigned size) > +{ > + std::stringstream dataStr; > + for (unsigned pos = 0; pos < size; pos++) { > + ccprintf(dataStr, "%02x", data[pos]); > + } > + return dataStr.str(); > +} > + > Tick > CacheUnit::CachePort::recvAtomic(PacketPtr pkt) > { > @@ -1057,6 +1067,7 @@ > DPRINTF(InOrderCachePort, > "[tid:%u]: [sn:%i]: Processing cache access\n", > tid, inst->seqNum); > + PacketPtr dataPkt = NULL; > > if (inst->splitInst) { > inst->splitFinishCnt++; > @@ -1078,11 +1089,12 @@ > split_pkt.dataStatic(&inst->storeData); > } > > - inst->completeAcc(&split_pkt); > + dataPkt = &split_pkt; > } > - } else { > - inst->completeAcc(pkt); > + } else { > + dataPkt = pkt; > } > + inst->completeAcc(dataPkt); > > if (inst->isLoad()) { > assert(cache_pkt->isRead()); > @@ -1094,21 +1106,19 @@ > TheISA::handleLockedRead(cpu, cache_pkt->req); > } > > - // @NOTE: Hardcoded to for load instructions. Assumes that > - // the dest. idx 0 is always where the data is loaded to. > DPRINTF(InOrderCachePort, > - "[tid:%u]: [sn:%i]: Data loaded was: %08p\n", > - tid, inst->seqNum, inst->readIntResult(0)); > - DPRINTF(InOrderCachePort, > - "[tid:%u]: [sn:%i]: FP Data loaded was: %08p\n", > - tid, inst->seqNum, inst->readFloatResult(0)); > + "[tid:%u]: [sn:%i]: Bytes loaded were: %s\n", > + tid, inst->seqNum, > + printMemData(dataPkt->getPtr<uint8_t>(), > + dataPkt->getSize())); > } else if(inst->isStore()) { > assert(cache_pkt->isWrite()); > > DPRINTF(InOrderCachePort, > - "[tid:%u]: [sn:%i]: Data stored was: FIX ME\n", > - tid, inst->seqNum/*, > - getMemData(cache_pkt)*/); > + "[tid:%u]: [sn:%i]: Bytes stored were: %s\n", > + tid, inst->seqNum, > + printMemData(dataPkt->getPtr<uint8_t>(), > + dataPkt->getSize())); > } > > delete cache_pkt; > @@ -1291,28 +1301,6 @@ > freeSlot(slot_remove_list[i]); > } > > -uint64_t > -CacheUnit::getMemData(Packet *packet) > -{ > - switch (packet->getSize()) > - { > - case 8: > - return packet->get<uint8_t>(); > - > - case 16: > - return packet->get<uint16_t>(); > - > - case 32: > - return packet->get<uint32_t>(); > - > - case 64: > - return packet->get<uint64_t>(); > - > - default: > - panic("bad store data size = %d\n", packet->getSize()); > - } > -} > - > // Extra Template Definitions > #ifndef DOXYGEN_SHOULD_SKIP_THIS > > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > -- - Korey
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