> On 2010-08-14 00:33:43, Gabe Black wrote: > > src/mem/cache/cache_impl.hh, line 561 > > <http://reviews.m5sim.org/r/192/diff/1/?file=1911#file1911line561> > > > > Don't comment out code, delete it. Why is this assert no longer needed? > > I don't know the cache code so I apologize if it's obvious.
This assertion checks that you don't have an uncacheable access to a block that's already in your cache, since there's no well-defined general behavior for that. I don't see how it's related to the stated goal of this patch, and I don't want to see it removed without some discussion about why it's wrong. - Steve ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/192/#review190 ----------------------------------------------------------- On 2010-08-13 10:16:34, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/192/ > ----------------------------------------------------------- > > (Updated 2010-08-13 10:16:34) > > > Review request for Default. > > > Summary > ------- > > ARM: Make sure that software prefetch instructions can't change the state of > the TLB > > > Diffs > ----- > > src/arch/arm/faults.hh 3c48b2b3cb83 > src/arch/arm/table_walker.cc 3c48b2b3cb83 > src/arch/arm/tlb.cc 3c48b2b3cb83 > src/mem/cache/cache_impl.hh 3c48b2b3cb83 > > Diff: http://reviews.m5sim.org/r/192/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
