> On 2010-10-21 13:35:21, Steve Reinhardt wrote: > > src/mem/protocol/MESI_CMP_directory-L1cache.sm, line 332 > > <http://reviews.m5sim.org/r/277/diff/1/?file=4455#file4455line332> > > > > This DPRINTF is broken (and several others like it)... it needs a trace > > flag as the first arg, and "%str" probably isn't the format string you want > > (basically it's just like printf, so you probably mean "%s").
The DPRINTF statements that appear in .sm files are re-written by the SLICC compiler. SLICC compiler provides the trace flag. Looking at the format specifier, the compiler will add a .c_str() after print_str(). But in a comment above, you mentioned that c_str() is not required. May be we can drop %str altogether. I need to look in to this. > On 2010-10-21 13:35:21, Steve Reinhardt wrote: > > src/mem/protocol/MESI_CMP_directory-L1cache.sm, line 333 > > <http://reviews.m5sim.org/r/277/diff/1/?file=4455#file4455line333> > > > > We should get rid of these commented-out lines, either deleting them if > > they're not needed or just using a trace flag that keeps them turned off > > unless wanted. That's the point of the trace flags, is so that you don't > > have to comment out debug printfs, but can just turn them on and off > > dynamically at the granularity you want. I can remove the commented lines, but I may not be the right person to make that decision. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/277/#review398 ----------------------------------------------------------- On 2010-10-19 17:30:48, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/277/ > ----------------------------------------------------------- > > (Updated 2010-10-19 17:30:48) > > > Review request for Default and Ruby Reviewers. > > > Summary > ------- > > Ruby currently uses GEMS debug support with the enum character string map to > enable certain debug messages. Meanwhile, M5 has debug print support that > works with scons. Compiling the m5.fast binary, the M5 debug statements are > removed, but the Ruby ones are not unless RUBY_DEBUG is not defined. This > patch moves Ruby to M5's debug print support. > > > Diffs > ----- > > src/cpu/testers/rubytest/CheckTable.cc 956ac83b0a58 > src/mem/SConscript 956ac83b0a58 > src/mem/protocol/MESI_CMP_directory-L1cache.sm 956ac83b0a58 > src/mem/protocol/MESI_CMP_directory-L2cache.sm 956ac83b0a58 > src/mem/protocol/MESI_CMP_directory-dir.sm 956ac83b0a58 > src/mem/protocol/MI_example-cache.sm 956ac83b0a58 > src/mem/protocol/MI_example-dir.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_directory-L2cache.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_directory-dir.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_directory-perfectDir.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_token-L1cache.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_token-L2cache.sm 956ac83b0a58 > src/mem/protocol/MOESI_CMP_token-dir.sm 956ac83b0a58 > src/mem/protocol/MOESI_hammer-cache.sm 956ac83b0a58 > src/mem/protocol/MOESI_hammer-dir.sm 956ac83b0a58 > src/mem/protocol/RubySlicc_Exports.sm 956ac83b0a58 > src/mem/protocol/RubySlicc_MemControl.sm 956ac83b0a58 > src/mem/protocol/RubySlicc_Types.sm 956ac83b0a58 > src/mem/ruby/SConsopts 956ac83b0a58 > src/mem/ruby/buffers/MessageBuffer.cc 956ac83b0a58 > src/mem/ruby/common/Address.hh 956ac83b0a58 > src/mem/ruby/common/DataBlock.hh 956ac83b0a58 > src/mem/ruby/common/Debug.hh 956ac83b0a58 > src/mem/ruby/common/Debug.cc 956ac83b0a58 > src/mem/ruby/common/NetDest.hh 956ac83b0a58 > src/mem/ruby/common/NetDest.cc 956ac83b0a58 > src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc > 956ac83b0a58 > src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc 956ac83b0a58 > src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc > 956ac83b0a58 > src/mem/ruby/network/garnet/flexible-pipeline/Router.cc 956ac83b0a58 > src/mem/ruby/network/simple/PerfectSwitch.cc 956ac83b0a58 > src/mem/ruby/network/simple/Throttle.cc 956ac83b0a58 > src/mem/ruby/network/simple/Topology.cc 956ac83b0a58 > src/mem/ruby/slicc_interface/Message.hh 956ac83b0a58 > src/mem/ruby/slicc_interface/NetworkMessage.hh 956ac83b0a58 > src/mem/ruby/storebuffer/storebuffer.cc 956ac83b0a58 > src/mem/ruby/system/CacheMemory.cc 956ac83b0a58 > src/mem/ruby/system/DirectoryMemory.cc 956ac83b0a58 > src/mem/ruby/system/SConscript 956ac83b0a58 > src/mem/ruby/system/SparseMemory.cc 956ac83b0a58 > src/mem/ruby/tester/RaceyPseudoThread.cc 956ac83b0a58 > src/mem/slicc/ast/FuncCallExprAST.py 956ac83b0a58 > src/mem/slicc/symbols/StateMachine.py 956ac83b0a58 > src/mem/slicc/symbols/Type.py 956ac83b0a58 > > Diff: http://reviews.m5sim.org/r/277/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
