> On 2010-12-22 14:35:28, Brad Beckmann wrote: > > Hi Nilay,
Could you please include the changes to the MOESI_CMP_directory protocol in this patch? It is difficult to understand the ramifications of these changes without seeing their impact to the .sm files. Also this is a very tricky patch and the holiday break is approaching, so please be patient. I will try to get you my feedback as soon as I can. Brad I am trying to add the MOESI_CMP_directory protocol patch separately. But apparently review board is not able to apply that patch cleanly. Take your time to review all the changes. -- Nilay - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/358/#review570 ----------------------------------------------------------- On 2010-12-22 14:21:09, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/358/ > ----------------------------------------------------------- > > (Updated 2010-12-22 14:21:09) > > > Review request for Default. > > > Summary > ------- > > The purpose of this patch is to change the way CacheMemory interfaces with > coherence protocols. Currently, whenever a cache controller (defined in the > protocol under consideration) needs to carry out any operation on a cache > block, it looks up the tag hash map and figures out whether or not the block > exists in the cache. In case it does exist, the operation is carried out > (which requires another lookup). Over a single clock cycle, multiple such > lookups take place as observed through profiling of different protocols. It > was seen that the tag lookup takes anything from 10% to 20% of the simulation > time. In order to reduce this time, this patch is being posted. The > CacheMemory class now will have a function that will return pointer to a > cache block entry, instead of a reference (though the function that returns > the reference has been retained currently). Functions have been introduced > for setting/unsetting a pointer and check its pointer. Similar changes have > been carried out for Transaction Buffer entries as well. > > Note that changes are required to both SLICC and the protocol files. This > patch carries out changes to SLICC and committing this patch alone, I > believe, will ___break___ all the protocols. I am working on patching the > protocols as well. This patch is being put to get feed back from other > developers. > > > Diffs > ----- > > src/mem/slicc/symbols/StateMachine.py 998b217dcae7 > src/mem/slicc/parser.py 998b217dcae7 > src/mem/slicc/symbols/Func.py 998b217dcae7 > src/mem/slicc/ast/StaticCastAST.py 998b217dcae7 > src/mem/slicc/ast/TypeDeclAST.py 998b217dcae7 > src/mem/slicc/ast/MethodCallExprAST.py 998b217dcae7 > src/mem/slicc/ast/InPortDeclAST.py 998b217dcae7 > src/mem/slicc/ast/FuncDeclAST.py 998b217dcae7 > src/mem/slicc/ast/FuncCallExprAST.py 998b217dcae7 > src/mem/slicc/ast/FormalParamAST.py 998b217dcae7 > src/mem/protocol/RubySlicc_Types.sm 998b217dcae7 > src/mem/ruby/slicc_interface/AbstractCacheEntry.hh 998b217dcae7 > src/mem/ruby/slicc_interface/AbstractCacheEntry.cc 998b217dcae7 > src/mem/ruby/system/CacheMemory.hh 998b217dcae7 > src/mem/ruby/system/CacheMemory.cc 998b217dcae7 > src/mem/ruby/system/TBETable.hh 998b217dcae7 > src/mem/slicc/ast/ActionDeclAST.py 998b217dcae7 > > Diff: http://reviews.m5sim.org/r/358/diff > > > Testing > ------- > > I have tested these changes using the MOESI_CMP_directory protocol. > > > Thanks, > > Nilay > >
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