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This is an automatically generated e-mail. To reply, visit:
http://reviews.m5sim.org/r/358/
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(Updated 2010-12-31 17:50:59.779517)


Review request for Default.


Changes
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1. lookup_ptr() function has been removed from CacheMemory class. Instead, 
lookup() function has been changed so that it returns a pointer to an 
AbstractCacheEntry, as opposed to a reference.

2. The manner in which the declaration of a CacheEntry structure in the 
protocol file is detected has been changed. Earlier detection was carried out 
using the name of the structure i.e. the structure should be named 'Entry' for 
the compiler to assume that it is the CacheEntry structure for that particular 
machine under consideration. Now, the check is made on the interface supplied 
with the structure declaration. It should be 'AbstractCacheEntry'. I think an 
assumption has been made that this would happen only once in the entire file. 
An error is raised if it happens more than once, though the error condition has 
not yet been tested.

3. While making changes to the MOESI Hammer protocol, I realized that the 
previously made changes to SLICC would not suffice. Earlier, the changes had 
been made under the assumption that at any given point of time, only one cache 
entry would be updated. But in the Hammer protocol, two cache entries can be 
processed in a single step. One of these would belong to L1 and the other to 
L2. I think the Hammer protocol could not have been supported with just one 
cache entry variable being passed to the trigger function. So, now the number 
of cache entries passed to the trigger function and subsequently to actions is 
same as the number of cache memories in the machine under consideration. This 
is two for MOESI_CMP_* and three for MOESI_hammer. Most of the changes that 
have been made since the previous version of the diff, are there to support 
because of the reason outlined above.


Summary
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The purpose of this patch is to change the way CacheMemory interfaces with 
coherence protocols. Currently, whenever a cache controller (defined in the 
protocol under consideration) needs to carry out any operation on a cache 
block, it looks up the tag hash map and figures out whether or not the block 
exists in the cache. In case it does exist, the operation is carried out (which 
requires another lookup). Over a single clock cycle, multiple such lookups take 
place as observed through profiling of different protocols. It was seen that 
the tag lookup takes anything from 10% to 20% of the simulation time. In order 
to reduce this time, this patch is being posted. The CacheMemory class now will 
have a function that will return pointer to a cache block entry, instead of a 
reference (though the function that returns the reference has been retained 
currently). Functions have been introduced for setting/unsetting a pointer and 
check its pointer. Similar changes have been carried out for Transaction Buffer 
entries as well.

Note that changes are required to both SLICC and the protocol files. This patch 
carries out changes to SLICC and committing this patch alone, I believe, will 
___break___ all the protocols. I am working on patching the protocols as well. 
This patch is being put to get feed back from other developers.


Diffs (updated)
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  src/mem/protocol/RubySlicc_Types.sm UNKNOWN 
  src/mem/ruby/slicc_interface/AbstractCacheEntry.hh UNKNOWN 
  src/mem/ruby/slicc_interface/AbstractCacheEntry.cc UNKNOWN 
  src/mem/ruby/system/CacheMemory.hh UNKNOWN 
  src/mem/ruby/system/CacheMemory.cc UNKNOWN 
  src/mem/ruby/system/TBETable.hh UNKNOWN 
  src/mem/slicc/ast/ActionDeclAST.py UNKNOWN 
  src/mem/slicc/ast/FormalParamAST.py UNKNOWN 
  src/mem/slicc/ast/FuncCallExprAST.py UNKNOWN 
  src/mem/slicc/ast/FuncDeclAST.py UNKNOWN 
  src/mem/slicc/ast/InPortDeclAST.py UNKNOWN 
  src/mem/slicc/ast/IsValidPtrExprAST.py PRE-CREATION 
  src/mem/slicc/ast/MethodCallExprAST.py UNKNOWN 
  src/mem/slicc/ast/StaticCastAST.py UNKNOWN 
  src/mem/slicc/ast/TypeDeclAST.py UNKNOWN 
  src/mem/slicc/ast/__init__.py UNKNOWN 
  src/mem/slicc/parser.py UNKNOWN 
  src/mem/slicc/symbols/StateMachine.py UNKNOWN 
  src/mem/slicc/symbols/SymbolTable.py UNKNOWN 

Diff: http://reviews.m5sim.org/r/358/diff


Testing
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I have tested these changes using the MOESI_CMP_directory and MI protocols.


Thanks,

Nilay

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