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src/mem/protocol/MOESI_hammer-cache.sm <http://reviews.m5sim.org/r/280/#comment826> There's a red blotch in reviewboard that I think is saying you have trailing space on this line. src/mem/protocol/MOESI_hammer-cache.sm <http://reviews.m5sim.org/r/280/#comment828> More functions where it would be nice to identify the one valid entry_ptr up front rather than passing all of the candidates in every time. Maybe this could even be pushed all the way back up to the set_cache_entry calls? I don't know enough about the protocols to know if that's feasible, but it sounds nice. - Steve On 2010-12-31 17:26:11, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/280/ > ----------------------------------------------------------- > > (Updated 2010-12-31 17:26:11) > > > Review request for Default. > > > Summary > ------- > > This request is for reviewing the updates made to the MOESI Hammer protocol > so that it conforms with the new interfaces of CacheMemory and TBETable > classes, and the changes in SLICC. > > > Diffs > ----- > > src/mem/protocol/MOESI_hammer-cache.sm UNKNOWN > src/mem/protocol/MOESI_hammer-dir.sm UNKNOWN > > Diff: http://reviews.m5sim.org/r/280/diff > > > Testing > ------- > > The changes have been tested using ruby_random_test.py for a 1,000,000 loads > and 20 different seed values. > > > Thanks, > > Nilay > >
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