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src/mem/protocol/MOESI_hammer-cache.sm <http://reviews.m5sim.org/r/280/#comment1013> Don't just comment out these lines. You should replace them with equivalent lines, such as: assert((is_valid(getL1DCacheEntry(addr) && is_valid(getL1ICacheEntry(add)) == false); ...etc. Since they are within the assert call, they should be compiled out for the ".fast" binary. - Brad On 2011-01-16 16:21:04, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/280/ > ----------------------------------------------------------- > > (Updated 2011-01-16 16:21:04) > > > Review request for Default. > > > Summary > ------- > > Ruby: Updates MOESI Hammer protocol > This patch updates the MOESI Hammer protocol to conform with the new > interfaces of CacheMemory and TBETable classes, and the changes in SLICC. > > > Diffs > ----- > > src/mem/protocol/MOESI_hammer-cache.sm 696063d6ed04 > src/mem/protocol/MOESI_hammer-dir.sm 696063d6ed04 > > Diff: http://reviews.m5sim.org/r/280/diff > > > Testing > ------- > > The changes have been tested using ruby_random_test.py for a 1,000,000 loads > and 20 different seed values. > > > Thanks, > > Nilay > >
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