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Ship it! I think we talked about this and I'm ok with what we ended up on the mailing list... Bonus points if you colorize the output :)... Blue = '\033[94m' Yellow = '\033[94m' Green = '\033[92m' End = '\0330m' CCCOMSTR = Blue + ' [ CC] ' + Yellow + '$TRANSFORMATION' + End - Ali On 2011-01-03 16:10:27, Steve Reinhardt wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/366/ > ----------------------------------------------------------- > > (Updated 2011-01-03 16:10:27) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > scons: show sources and targets when building. > > I like the brevity of Ali's recent change, but the ambiguity of > sometimes showing the source and sometimes the target is a little > confusing. This patch makes scons typically list all sources and > all targets for each action, with the common path prefix factored > out for brevity. It's a little more verbose now but also more > informative. > > I'm not intending to add this to the commit message, but for review purposes, > here's some example output: > [ CXX] ALPHA_SE/sim: main.cc -> main.do > Defining FAST_ALLOC_DEBUG as 0 in build/ALPHA_SE/config/fast_alloc_debug.hh. > Defining FAST_ALLOC_STATS as 0 in build/ALPHA_SE/config/fast_alloc_stats.hh. > Defining NO_FAST_ALLOC as 0 in build/ALPHA_SE/config/no_fast_alloc.hh. > [ TRACING] ALPHA_SE/base: -> traceflags.hh > [ CXX] ALPHA_SE/python/swig: pyevent.cc -> pyevent.do > Defining FULL_SYSTEM as 0 in build/ALPHA_SE/config/full_system.hh. > [SO PARAM] MemObject -> ALPHA_SE/params/MemObject.hh > [SO PARAM] SimObject -> ALPHA_SE/params/SimObject.hh > [GENERATE] ALPHA_SE/arch: -> isa_traits.hh > [ CXX] ALPHA_SE/python/swig: pyobject.cc -> pyobject.do > [ SWIG] ALPHA_SE/python/swig: core.i -> core_wrap.cc, core.py > [ CXX] ALPHA_SE/python/swig: core_wrap.cc -> core_wrap.do > [ SWIG] ALPHA_SE/python/swig: debug.i -> debug_wrap.cc, debug.py > [ CXX] ALPHA_SE/python/swig: debug_wrap.cc -> debug_wrap.do > (...skipping...) > [GENERATE] ALPHA_SE/arch: -> vtophys.hh > [ CFG ISA] alpha, arm, mips, no, power, sparc, x86 -> > ALPHA_SE/config/the_isa.hh > [GENERATE] ALPHA_SE/arch: -> types.hh > [GENERATE] ALPHA_SE/arch: -> registers.hh > [GENERATE] static_inst_exec_sigs.hh: AtomicSimpleCPU, InOrderCPU, O3CPU, > TimingSimpleCPU > [EN PARAM] MemoryMode -> ALPHA_SE/enums/MemoryMode.hh > [SO PARAM] System -> ALPHA_SE/params/System.hh > [EN PARAM] OpClass -> ALPHA_SE/enums/OpClass.hh > [SO PARAM] PhysicalMemory -> ALPHA_SE/params/PhysicalMemory.hh > [ISA DESC] ALPHA_SE/arch/alpha: isa/main.isa -> decoder.cc, decoder.hh, > max_inst_regs.hh, atomic_simple_cpu_exec.cc, inorder_cpu_exec.cc, > o3_cpu_exec.cc, timing_simple_cpu_exec.cc > [ CXX] ALPHA_SE/base: remote_gdb.cc -> remote_gdb.do > [ CXX] ALPHA_SE/base: socket.cc -> socket.do > (...skipping...) > [SW PARAM] Process -> ALPHA_SE/python/m5/internal/vptype_Process.i > [BLDPARAM] Process -> ALPHA_SE/python/m5/internal/param_Process.i > [BLDPARAM] SimObject -> ALPHA_SE/python/m5/internal/param_SimObject.i > [BLDPARAM] System -> ALPHA_SE/python/m5/internal/param_System.i > [ENUMSWIG] MemoryMode -> ALPHA_SE/python/m5/internal/enum_MemoryMode.i > [BLDPARAM] PhysicalMemory -> > ALPHA_SE/python/m5/internal/param_PhysicalMemory.i > [BLDPARAM] MemObject -> ALPHA_SE/python/m5/internal/param_MemObject.i > [ SWIG] ALPHA_SE/python/m5/internal: vptype_Process.i -> > vptype_Process_wrap.cc, vptype_Process.py > [ CXX] ALPHA_SE/python/m5/internal: vptype_Process_wrap.cc -> > vptype_Process_wrap.do > [SW PARAM] AddrRange -> ALPHA_SE/python/m5/internal/vptype_AddrRange.i > [ SWIG] ALPHA_SE/python/m5/internal: vptype_AddrRange.i -> > vptype_AddrRange_wrap.cc, vptype_AddrRange.py > [ CXX] ALPHA_SE/python/m5/internal: vptype_AddrRange_wrap.cc -> > vptype_AddrRange_wrap.do > (...skipping...) > [EMBED PY] ALPHA_SE/python/m5/internal: param_BaseSimpleCPU.py -> > param_BaseSimpleCPU.py.cc > [ CXX] ALPHA_SE/python/m5/internal: param_BaseSimpleCPU.py.cc -> > param_BaseSimpleCPU.py.do > [EMBED PY] ALPHA_SE/python/m5/internal: param_LiveProcess.py -> > param_LiveProcess.py.cc > [ CXX] ALPHA_SE/python/m5/internal: param_LiveProcess.py.cc -> > param_LiveProcess.py.do > [ TRACING] ALPHA_SE/base: -> traceflags.py > [EMBED PY] ALPHA_SE/base: traceflags.py -> traceflags.py.cc > [ CXX] ALPHA_SE/base: traceflags.py.cc -> traceflags.py.do > [ CXX] ALPHA_SE/base: date.cc -> date.do > [ LINK] ALPHA_SE: -> m5.debug > > > Diffs > ----- > > SConstruct 7338bc628489 > src/SConscript 7338bc628489 > src/arch/SConscript 7338bc628489 > src/arch/isa_parser.py 7338bc628489 > > Diff: http://reviews.m5sim.org/r/366/diff > > > Testing > ------- > > quick regressions pass > > > Thanks, > > Steve > >
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