> On 2011-01-07 04:32:37, Gabe Black wrote: > > There are a few problems with this. First, this is an indirect way to get > > around the problem. It looks like IntDev can be constructed with no latency > > argument which defaults to 0 which is why the call to sendTiming/schedule > > would fail. A better fix would be to pass the right latency to the > > constructor of IntDev so it has the right value as apposed to passing it in > > when needed (ignoring the stored value as well). Second, the latency being > > used in interrupts.cc is actually the pio_latency which is the latency for > > accessing the memory mapped registers in the local APIC. This is not > > necessarily the latency that should be used for sending interrupts. It > > looks like the IO APIC has an int_latency parameter, and it would make > > sense to put one on the local APIC too. Bringing it all around, that would > > then go to the IntDev constructor.
Here, I think you're discussing a bigger problem than this patch is trying to fix. This patch simply passes the latency of the component to the port, which schedules the outgoing packet analogously to the SimpleTimingPort as defined in tport.*. Where that latency value actually comes from is a completely different question that seemed more straightforward when I originally made the changes. I think you're right that the IntDev (but NOT the IntPort), should have a latency data member that is inherited by the descendant classes (Interrupts, I8259 and I82094AA - each class has it's own latency member), and that data member should be set in their constructors. I'd have to default to you about whether any of these devices should be assessing a different latency for certain types of transactions. - Joel ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/383/#review640 ----------------------------------------------------------- On 2011-01-06 15:56:44, Brad Beckmann wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/383/ > ----------------------------------------------------------- > > (Updated 2011-01-06 15:56:44) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > IntDev: packet latency fix > > The IntDev should be responsible for setting the latency of packets sent > through it's port. This patch fixes the packet scheduling failure when the > IntPort latency is 0 in timing mode. > > > Diffs > ----- > > src/arch/x86/interrupts.cc 9f9e10967912 > src/dev/x86/i82094aa.cc 9f9e10967912 > src/dev/x86/intdev.hh 9f9e10967912 > src/dev/x86/intdev.cc 9f9e10967912 > > Diff: http://reviews.m5sim.org/r/383/diff > > > Testing > ------- > > > Thanks, > > Brad > >
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