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src/cpu/o3/commit_impl.hh <http://reviews.m5sim.org/r/338/#comment984> I split this into two functions, but boolean is if interrupt == NoFault or not. The flow control is much better and after it passes regressions I'll post it. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/338/#comment985> Moved the check into fetchCacheLine. No ugly macros, but there still is an alpha specific bit src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/338/#comment986> merged src/cpu/o3/iew_impl.hh <http://reviews.m5sim.org/r/338/#comment987> yup - Ali On 2010-12-06 16:10:48, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/338/ > ----------------------------------------------------------- > > (Updated 2010-12-06 16:10:48) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fixes fetch deadlock when the interrupt master clears single before CPU > handles it. > Then the cpu should restart fetch stage to fetch from the original execution > path. > > > Diffs > ----- > > src/arch/arm/interrupts.hh 2b5fbdcbfb5d > src/cpu/o3/commit_impl.hh 2b5fbdcbfb5d > src/cpu/o3/fetch_impl.hh 2b5fbdcbfb5d > src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d > > Diff: http://reviews.m5sim.org/r/338/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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