----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/338/ -----------------------------------------------------------
(Updated 2011-01-12 09:06:31.556839) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary (updated) ------- O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propigates appropriately. Diffs (updated) ----- src/arch/arm/interrupts.hh 5d0f62927d75 src/cpu/o3/commit.hh 5d0f62927d75 src/cpu/o3/commit_impl.hh 5d0f62927d75 src/cpu/o3/fetch.hh 5d0f62927d75 src/cpu/o3/fetch_impl.hh 5d0f62927d75 src/cpu/o3/iew_impl.hh 5d0f62927d75 Diff: http://reviews.m5sim.org/r/338/diff Testing ------- Thanks, Ali
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