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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- O3: Enhance data address translation by supporting hardware page table walkers. Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution. Diffs ----- src/arch/arm/tlb.cc 5d0f62927d75 src/cpu/base_dyn_inst.hh 5d0f62927d75 src/cpu/base_dyn_inst_impl.hh 5d0f62927d75 src/cpu/o3/fetch.hh 5d0f62927d75 src/cpu/o3/iew_impl.hh 5d0f62927d75 src/cpu/o3/inst_queue.hh 5d0f62927d75 src/cpu/o3/inst_queue_impl.hh 5d0f62927d75 src/cpu/o3/lsq_unit_impl.hh 5d0f62927d75 src/cpu/simple/timing.hh 5d0f62927d75 src/cpu/translation.hh 5d0f62927d75 src/sim/tlb.hh 5d0f62927d75 Diff: http://reviews.m5sim.org/r/422/diff Testing ------- Thanks, Ali
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