Hi Nilay, My plan is to tackle the functional access support as soon as I check in our current group of outstanding patches. I'm hoping to at least check in the majority of them in the next couple of days. Now that you've completed the CacheMemory access changes, you may want to re-profile GEM5 and make sure the next performance bottleneck is routing network messages in the Perfect Switch. In particular, you'll want to look at rather large (16+ core) systems using a standard Mesh network. If you have any questions on how to do that, Arka may be able to help you out, if not, I can certainly help you. Assuming the Perfect Switch shows up as a major bottleneck (> 10%), then I would suggest that as the next area you can work on. When looking at possible solutions, don't limit yourself to just changes within Perfect Switch itself. I suspect that redesigning how destinations are encoded and/or the interface between MessageBuffer dequeues and the PerfectSwitch wakeup, will lead to a b etter solution.
Brad > -----Original Message----- > From: Nilay Vaish [mailto:[email protected]] > Sent: Tuesday, January 18, 2011 6:59 AM > To: Beckmann, Brad > Cc: [email protected] > Subject: > > Hi Brad > > Now that those changes to CacheMemory, SLICC and protocol files have > been pushed in, what's next that you think we should work on? I was going > through some of the earlier emails. You have mentioned functional access > support in Ruby, design of the Perfect Switch, consolidation of stat files. > > Thanks > Nilay _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
