Quoting Steve Reinhardt <ste...@gmail.com>:
Gabe, how many bytes at a time does the x86 predecoder fetch? If it doesn't currently grab a cache line at a time, could it be made to do so, and do you know if that would cause any issues with SMC?
All of the predecoders expect to receive one MachInst at a time so that for fixed width ISAs they naturally get one instruction at a time. For x86 that type doesn't really mean anything other than controlling that width. Currently it's defined to be a uint64_t, but that could be changed pretty easily with hopefully basically no functional effect. Whatever it is would need to have some integer like properties, though, where it could be shifted, masked, etc. I have it set to a big int to try to minimize trips through the predecoder, the work needed to glue big immediates together, etc.
I heard during a presentation by a pretty senior VMware guy that x86 isn't guaranteed to refetch instruction bytes until a control flow instruction and/or a serializing instruction or something along those lines. A former AMD guy in the room was surprised by that, though, so I'm not sure it's true. It could be one of those things that's supposed to be true, but to get minesweeper to work on Windows 95 they have to refetch anyway. It could also be a difference between Intel and AMD. So the take away answer is possibly no, possibly yes.
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