changeset 8b05ff5ef958 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=8b05ff5ef958
description:
IntDev: packet latency fix
The x86 local apic now includes a separate latency parameter for
interrupts.
diffstat:
src/arch/x86/X86LocalApic.py | 2 ++
src/arch/x86/interrupts.cc | 3 ++-
2 files changed, 4 insertions(+), 1 deletions(-)
diffs (22 lines):
diff -r 38eca2df1124 -r 8b05ff5ef958 src/arch/x86/X86LocalApic.py
--- a/src/arch/x86/X86LocalApic.py Sun Feb 06 22:14:17 2011 -0800
+++ b/src/arch/x86/X86LocalApic.py Sun Feb 06 22:14:17 2011 -0800
@@ -34,3 +34,5 @@
cxx_class = 'X86ISA::Interrupts'
pio_latency = Param.Latency('1ns', 'Programmed IO latency in simticks')
int_port = Port("Port for sending and receiving interrupt messages")
+ int_latency = Param.Latency('1ns', \
+ "Latency for an interrupt to propagate through this device.")
diff -r 38eca2df1124 -r 8b05ff5ef958 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Sun Feb 06 22:14:17 2011 -0800
+++ b/src/arch/x86/interrupts.cc Sun Feb 06 22:14:17 2011 -0800
@@ -595,7 +595,8 @@
X86ISA::Interrupts::Interrupts(Params * p) :
- BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
+ BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency),
+ clock(0),
apicTimerEvent(this),
pendingSmi(false), smiVector(0),
pendingNmi(false), nmiVector(0),
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