changeset 7532067f818e in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=7532067f818e
description:
ruby: support to stallAndWait the mandatory queue
By stalling and waiting the mandatory queue instead of recycling it,
one can
ensure that no incoming messages are starved when the mandatory queue
puts
signficant of pressure on the L1 cache controller (i.e. the ruby
memtester).
diffstat:
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 207 +++++++++++-------
src/mem/protocol/MOESI_hammer-cache.sm | 123 +++++++----
src/mem/ruby/buffers/MessageBuffer.cc | 36 +++-
src/mem/ruby/buffers/MessageBuffer.hh | 1 +
src/mem/slicc/ast/WakeUpAllDependentsStatementAST.py | 43 +++
src/mem/slicc/ast/__init__.py | 1 +
src/mem/slicc/parser.py | 5 +
src/mem/slicc/symbols/StateMachine.py | 32 ++
8 files changed, 318 insertions(+), 130 deletions(-)
diffs (truncated from 1006 to 300 lines):
diff -r 351f1761765f -r 7532067f818e src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Feb 06 22:14:19
2011 -0800
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Feb 06 22:14:19
2011 -0800
@@ -433,7 +433,7 @@
// ** IN_PORTS **
// Use Timer
- in_port(useTimerTable_in, Address, useTimerTable) {
+ in_port(useTimerTable_in, Address, useTimerTable, rank=5) {
if (useTimerTable_in.isReady()) {
TBE tbe := L1_TBEs[useTimerTable.readyAddress()];
@@ -459,7 +459,7 @@
}
// Reissue Timer
- in_port(reissueTimerTable_in, Address, reissueTimerTable) {
+ in_port(reissueTimerTable_in, Address, reissueTimerTable, rank=4) {
if (reissueTimerTable_in.isReady()) {
trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(),
getCacheEntry(reissueTimerTable.readyAddress()),
@@ -467,10 +467,8 @@
}
}
-
-
// Persistent Network
- in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache) {
+ in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) {
if (persistentNetwork_in.isReady()) {
peek(persistentNetwork_in, PersistentMsg, block_on="Address") {
assert(in_msg.Destination.isElement(machineID));
@@ -519,6 +517,77 @@
}
}
+ // Response Network
+ in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) {
+ if (responseNetwork_in.isReady()) {
+ peek(responseNetwork_in, ResponseMsg, block_on="Address") {
+ assert(in_msg.Destination.isElement(machineID));
+
+ Entry cache_entry := getCacheEntry(in_msg.Address);
+ TBE tbe := L1_TBEs[in_msg.Address];
+
+ // Mark TBE flag if response received off-chip. Use this to update
average latency estimate
+ if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
+
+ if (in_msg.Sender == mapAddressToRange(in_msg.Address,
+ MachineType:L2Cache,
+ l2_select_low_bit,
+ l2_select_num_bits)) {
+
+ // came from an off-chip L2 cache
+ if (is_valid(tbe)) {
+ // L1_TBEs[in_msg.Address].ExternalResponse := true;
+ // profile_offchipL2_response(in_msg.Address);
+ }
+ }
+ else {
+ // profile_onchipL2_response(in_msg.Address );
+ }
+ } else if ( machineIDToMachineType(in_msg.Sender) ==
MachineType:Directory ) {
+ if (is_valid(tbe)) {
+ setExternalResponse(tbe);
+ // profile_memory_response( in_msg.Address);
+ }
+ } else if ( machineIDToMachineType(in_msg.Sender) ==
MachineType:L1Cache) {
+ //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
+ //if (is_valid(tbe)) {
+ // tbe.ExternalResponse := true;
+ // profile_offchipL1_response(in_msg.Address );
+ //}
+ //}
+ //else {
+ // profile_onchipL1_response(in_msg.Address );
+ //}
+ } else {
+ error("unexpected SenderMachine");
+ }
+
+
+ if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
+ if (in_msg.Type == CoherenceResponseType:ACK) {
+ assert(in_msg.Tokens < (max_tokens() / 2));
+ trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
+ trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
+ assert(in_msg.Tokens < (max_tokens() / 2));
+ trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
+ } else {
+ error("Unexpected message");
+ }
+ } else {
+ if (in_msg.Type == CoherenceResponseType:ACK) {
+ assert(in_msg.Tokens < (max_tokens() / 2));
+ trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
+ } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER ||
in_msg.Type == CoherenceResponseType:DATA_SHARED) {
+ trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
+ } else {
+ error("Unexpected message");
+ }
+ }
+ }
+ }
+ }
// Request Network
in_port(requestNetwork_in, RequestMsg, requestToL1Cache) {
@@ -567,80 +636,8 @@
}
}
- // Response Network
- in_port(responseNetwork_in, ResponseMsg, responseToL1Cache) {
- if (responseNetwork_in.isReady()) {
- peek(responseNetwork_in, ResponseMsg, block_on="Address") {
- assert(in_msg.Destination.isElement(machineID));
-
- Entry cache_entry := getCacheEntry(in_msg.Address);
- TBE tbe := L1_TBEs[in_msg.Address];
-
- // Mark TBE flag if response received off-chip. Use this to update
average latency estimate
- if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
-
- if (in_msg.Sender == mapAddressToRange(in_msg.Address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits)) {
-
- // came from an off-chip L2 cache
- if (is_valid(tbe)) {
- // L1_TBEs[in_msg.Address].ExternalResponse := true;
- // profile_offchipL2_response(in_msg.Address);
- }
- }
- else {
- // profile_onchipL2_response(in_msg.Address );
- }
- } else if ( machineIDToMachineType(in_msg.Sender) ==
MachineType:Directory ) {
- if (is_valid(tbe)) {
- setExternalResponse(tbe);
- // profile_memory_response( in_msg.Address);
- }
- } else if ( machineIDToMachineType(in_msg.Sender) ==
MachineType:L1Cache) {
- //if (isLocalProcessor(machineID, in_msg.Sender) == false) {
- //if (is_valid(tbe)) {
- // tbe.ExternalResponse := true;
- // profile_offchipL1_response(in_msg.Address );
- //}
- //}
- //else {
- // profile_onchipL1_response(in_msg.Address );
- //}
- } else {
- error("unexpected SenderMachine");
- }
-
-
- if (getTokens(cache_entry) + in_msg.Tokens != max_tokens()) {
- if (in_msg.Type == CoherenceResponseType:ACK) {
- assert(in_msg.Tokens < (max_tokens() / 2));
- trigger(Event:Ack, in_msg.Address, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER) {
- trigger(Event:Data_Owner, in_msg.Address, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceResponseType:DATA_SHARED) {
- assert(in_msg.Tokens < (max_tokens() / 2));
- trigger(Event:Data_Shared, in_msg.Address, cache_entry, tbe);
- } else {
- error("Unexpected message");
- }
- } else {
- if (in_msg.Type == CoherenceResponseType:ACK) {
- assert(in_msg.Tokens < (max_tokens() / 2));
- trigger(Event:Ack_All_Tokens, in_msg.Address, cache_entry, tbe);
- } else if (in_msg.Type == CoherenceResponseType:DATA_OWNER ||
in_msg.Type == CoherenceResponseType:DATA_SHARED) {
- trigger(Event:Data_All_Tokens, in_msg.Address, cache_entry, tbe);
- } else {
- error("Unexpected message");
- }
- }
- }
- }
- }
-
// Mandatory Queue
- in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
+ in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...", rank=0) {
if (mandatoryQueue_in.isReady()) {
peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
// Check for data access to blocks in I-cache and ifetchs to blocks in
D-cache
@@ -1339,6 +1336,11 @@
tbe.IssueTime := get_time();
}
+ action(ta_traceStalledAddress, "ta", desc="Trace Stalled Address") {
+ peek(mandatoryQueue_in, CacheMsg) {
+ APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
+ }
+ }
action(j_unsetReissueTimer, "j", desc="Unset reissue timer.") {
if (reissueTimerTable.isSet(address)) {
@@ -1527,8 +1529,19 @@
}
}
- action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory
queue to the back of the queue.") {
- mandatoryQueue_in.recycle();
+ action(zz_stallAndWaitMandatoryQueue, "\z", desc="Send the head of the
mandatory queue to the back of the queue.") {
+ peek(mandatoryQueue_in, CacheMsg) {
+ APPEND_TRANSITION_COMMENT(in_msg.LineAddress);
+ }
+ stall_and_wait(mandatoryQueue_in, address);
+ }
+
+ action(kd_wakeUpDependents, "kd", desc="wake-up dependents") {
+ wake_up_dependents(address);
+ }
+
+ action(ka_wakeUpAllDependents, "ka", desc="wake-up all dependents") {
+ wake_up_all_dependents();
}
//*****************************************************
@@ -1537,15 +1550,16 @@
// Transitions for Load/Store/L2_Replacement from transient states
transition({IM, SM, OM, IS, IM_L, IS_L, I_L, S_L, SM_L, M_W, MM_W},
L1_Replacement) {
- zz_recycleMandatoryQueue;
+ ta_traceStalledAddress;
+ zz_stallAndWaitMandatoryQueue;
}
transition({IM, SM, OM, IS, IM_L, IS_L, SM_L}, {Store, Atomic}) {
- zz_recycleMandatoryQueue;
+ zz_stallAndWaitMandatoryQueue;
}
transition({IM, IS, IM_L, IS_L}, {Load, Ifetch}) {
- zz_recycleMandatoryQueue;
+ zz_stallAndWaitMandatoryQueue;
}
@@ -1615,8 +1629,10 @@
}
transition(I, L1_Replacement) {
+ ta_traceStalledAddress;
tr_tokenReplacement;
gg_deallocateL1CacheBlock;
+ ka_wakeUpAllDependents;
}
transition(I, {Transient_GETX, Transient_Local_GETX}) {
@@ -1674,8 +1690,10 @@
}
transition(S, L1_Replacement, I) {
+ ta_traceStalledAddress;
cc_sharedReplacement; // Only needed in some cases
gg_deallocateL1CacheBlock;
+ ka_wakeUpAllDependents;
}
transition(S, {Transient_GETX, Transient_Local_GETX}, I) {
@@ -1750,8 +1768,10 @@
}
transition(O, L1_Replacement, I) {
+ ta_traceStalledAddress;
c_ownedReplacement;
gg_deallocateL1CacheBlock;
+ ka_wakeUpAllDependents;
}
transition(O, {Transient_GETX, Transient_Local_GETX}, I) {
@@ -1835,8 +1855,10 @@
}
transition(MM, L1_Replacement, I) {
+ ta_traceStalledAddress;
c_ownedReplacement;
gg_deallocateL1CacheBlock;
+ ka_wakeUpAllDependents;
}
transition(MM, {Transient_GETX, Transient_Local_GETX, Transient_GETS,
Transient_Local_GETS}, I) {
@@ -1864,11 +1886,13 @@
transition(MM_W, Use_TimeoutNoStarvers, MM) {
s_deallocateTBE;
jj_unsetUseTimer;
+ kd_wakeUpDependents;
}
transition(MM_W, Use_TimeoutNoStarvers_NoMig, M) {
s_deallocateTBE;
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