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(Updated 2011-02-07 03:27:33.376190) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Changes ------- Updating diff as per suggestions from Gabe -- flip t1 & t2 in JMP_FAR_I (not jmpFarWork), introduce badWrite temporary. Summary ------- X86: ISA bug fixes identified when bringing up Barrelfish on M5. (#1) During iret access LDT/GDT at CPL0 rather than after transition to user mode (if I'm reading the Intel IA-64 architecture spec correctly, the contents of the descriptor table are read before the CPL is updated). (#2) During JMP_FAR_I, use srl to extract the segment selector from the top of the destination. (#3) Switch use of t1 and t2 inputs in jmpFarWork (which was inconsistent with call from JMP_FAR_I) (#4) During SYSCALL_64, use dataSize=8 when handling new rip (ref http://www.intel.com/Assets/PDF/manual/253668.pdf 5.8.8 IA32_LSTAR is a 64-bit address), (#5) If cr0.wp ("write protect" bit) is clear then do not generate page faults when writing to write-protected pages in kernel mode. I'm not sure I've got the correct fix for #3. I see there are other calls into jmpFarWork from JMP_FAR_M&P. I'm not sure I understand what these are doing, so I'm worried that I've either missed consequential changes to the use of t1/t2 somewhere (or that the correct fix is to modify JMP_FAR_I rather tahn jmpFarWork). Diffs (updated) ----- src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py 2c2dc567a450 src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py 2c2dc567a450 src/arch/x86/isa/insts/general_purpose/system_calls.py 2c2dc567a450 src/arch/x86/tlb.cc 2c2dc567a450 Diff: http://reviews.m5sim.org/r/467/diff Testing ------- Thanks, Tim
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