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src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/480/#comment1221> I don't think this stat is very useful, and it adds an extra point of divergence for stats in the future and means they'll all have to be rerun for O3. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/480/#comment1219> This vaddr check seems dangerous. There's nothing I'm aware of that ensures two different requests won't have the same vaddr. src/cpu/o3/fetch_impl.hh <http://reviews.m5sim.org/r/480/#comment1220> Don't add random blank lines. - Gabe On 2011-02-11 16:47:16, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/480/ > ----------------------------------------------------------- > > (Updated 2011-02-11 16:47:16) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fix bug when a squash occurs right before TLB miss returns. > > In this case we need to throw away the TLB miss, not assume it was the > one we were waiting for. > > > Diffs > ----- > > src/cpu/o3/fetch.hh 6548721032fa > src/cpu/o3/fetch_impl.hh 6548721032fa > > Diff: http://reviews.m5sim.org/r/480/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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