> On 2011-02-11 23:19:23, Gabe Black wrote: > > src/cpu/o3/fetch_impl.hh, line 271 > > <http://reviews.m5sim.org/r/480/diff/1/?file=10306#file10306line271> > > > > I don't think this stat is very useful, and it adds an extra point of > > divergence for stats in the future and means they'll all have to be rerun > > for O3.
It mirrors a fetchIcacheSquash stat we have and I think it's interesting to know how many times a translation was ended by a branch mispredict. > On 2011-02-11 23:19:23, Gabe Black wrote: > > src/cpu/o3/fetch_impl.hh, line 619 > > <http://reviews.m5sim.org/r/480/diff/1/?file=10306#file10306line619> > > > > This vaddr check seems dangerous. There's nothing I'm aware of that > > ensures two different requests won't have the same vaddr. The point is to verify that the translation we got back is actually the one we requested. It slices the bug and breaks nothing. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/480/#review852 ----------------------------------------------------------- On 2011-02-11 16:47:16, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/480/ > ----------------------------------------------------------- > > (Updated 2011-02-11 16:47:16) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fix bug when a squash occurs right before TLB miss returns. > > In this case we need to throw away the TLB miss, not assume it was the > one we were waiting for. > > > Diffs > ----- > > src/cpu/o3/fetch.hh 6548721032fa > src/cpu/o3/fetch_impl.hh 6548721032fa > > Diff: http://reviews.m5sim.org/r/480/diff > > > Testing > ------- > > > Thanks, > > Ali > >
_______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
