changeset 9c040d644df1 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=9c040d644df1 description: inorder: utilize cached skeds in pipeline allow the pipeline and resources to use the cached instruction schedule and resource sked iterator
diffstat: src/cpu/inorder/SConscript | 2 +- src/cpu/inorder/cpu.cc | 19 +++++- src/cpu/inorder/first_stage.cc | 2 +- src/cpu/inorder/inorder_dyn_inst.cc | 4 +- src/cpu/inorder/inorder_dyn_inst.hh | 92 ++++++++++++++++++--------- src/cpu/inorder/pipeline_stage.cc | 11 ++- src/cpu/inorder/resource.cc | 4 +- src/cpu/inorder/resource_pool.cc | 11 +++ src/cpu/inorder/resource_pool.hh | 2 + src/cpu/inorder/resource_sked.cc | 78 +++++++++++++++-------- src/cpu/inorder/resources/cache_unit.cc | 20 +++-- src/cpu/inorder/resources/decode_unit.cc | 7 +- src/cpu/inorder/resources/fetch_unit.cc | 6 +- src/cpu/inorder/resources/graduation_unit.cc | 5 +- src/cpu/inorder/resources/mult_div_unit.cc | 6 +- src/cpu/inorder/resources/tlb_unit.cc | 2 +- src/cpu/inorder/resources/use_def.cc | 6 +- 17 files changed, 188 insertions(+), 89 deletions(-) diffs (truncated from 695 to 300 lines): diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/SConscript --- a/src/cpu/inorder/SConscript Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/SConscript Sat Feb 12 10:14:45 2011 -0500 @@ -55,7 +55,7 @@ TraceFlag('ThreadModel') TraceFlag('RefCount') TraceFlag('AddrDep') - + TraceFlag('SkedCache') CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU', 'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred', diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/cpu.cc --- a/src/cpu/inorder/cpu.cc Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/cpu.cc Sat Feb 12 10:14:45 2011 -0500 @@ -368,7 +368,7 @@ RSkedPtr InOrderCPU::createFrontEndSked() { - RSkedPtr res_sked = NULL; + RSkedPtr res_sked = new ResourceSked(); int stage_num = 0; StageScheduler F(res_sked, stage_num++); StageScheduler D(res_sked, stage_num++); @@ -383,6 +383,9 @@ D.needs(BPred, BranchPredictor::PredictBranch); D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC); + + DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n"); + return res_sked; } @@ -391,7 +394,11 @@ { RSkedPtr res_sked = lookupSked(inst); if (res_sked != NULL) { + DPRINTF(SkedCache, "Found %s in sked cache.\n", + inst->instName()); return res_sked; + } else { + res_sked = new ResourceSked(); } int stage_num = ThePipeline::BackEndStartStage; @@ -402,7 +409,7 @@ if (!inst->staticInst) { warn_once("Static Instruction Object Not Set. Can't Create" " Back End Schedule"); - return false; + return NULL; } // EXECUTE @@ -458,6 +465,14 @@ W.needs(Grad, GraduationUnit::GraduateInst); + // Insert Front Schedule into our cache of + // resource schedules + addToSkedCache(inst, res_sked); + + DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n", + inst->instName(), inst->getMachInst()); + res_sked->print(); + return res_sked; } diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/first_stage.cc --- a/src/cpu/inorder/first_stage.cc Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/first_stage.cc Sat Feb 12 10:14:45 2011 -0500 @@ -181,7 +181,7 @@ inst->setInstListIt(cpu->addInst(inst)); // Create Front-End Resource Schedule For Instruction - ThePipeline::createFrontEndSchedule(inst); + inst->setFrontSked(cpu->frontEndSked); } int reqs_processed = 0; diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/inorder_dyn_inst.cc --- a/src/cpu/inorder/inorder_dyn_inst.cc Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/inorder_dyn_inst.cc Sat Feb 12 10:14:45 2011 -0500 @@ -51,7 +51,7 @@ const TheISA::PCState &instPC, const TheISA::PCState &_predPC, InstSeqNum seq_num, InOrderCPU *cpu) - : staticInst(machInst, instPC.instAddr()), traceData(NULL), cpu(cpu) + : staticInst(machInst, instPC.instAddr()), traceData(NULL), cpu(cpu) { seqNum = seq_num; @@ -108,6 +108,8 @@ void InOrderDynInst::initVars() { + inFrontEnd = true; + fetchMemReq = NULL; dataMemReq = NULL; splitMemData = NULL; diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/inorder_dyn_inst.hh --- a/src/cpu/inorder/inorder_dyn_inst.hh Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/inorder_dyn_inst.hh Sat Feb 12 10:14:45 2011 -0500 @@ -337,8 +337,9 @@ //////////////////////////////////////////////////////////// std::string instName() { return staticInst->getName(); } + void setMachInst(ExtMachInst inst); - void setMachInst(ExtMachInst inst); + ExtMachInst getMachInst() { return staticInst->machInst; } /** Sets the StaticInst. */ void setStaticInst(StaticInstPtr &static_inst); @@ -411,6 +412,39 @@ // RESOURCE SCHEDULING // ///////////////////////////////////////////// + typedef ThePipeline::RSkedPtr RSkedPtr; + bool inFrontEnd; + + RSkedPtr frontSked; + RSkedIt frontSked_end; + + RSkedPtr backSked; + RSkedIt backSked_end; + + RSkedIt curSkedEntry; + + void setFrontSked(RSkedPtr front_sked) + { + frontSked = front_sked; + frontSked_end.init(frontSked); + frontSked_end = frontSked->end(); + //DPRINTF(InOrderDynInst, "Set FrontSked End to : %x \n" , + // frontSked_end.getIt()/*, frontSked->end()*/); + //assert(frontSked_end == frontSked->end()); + + // This initializes instruction to be able + // to walk the resource schedule + curSkedEntry.init(frontSked); + curSkedEntry = frontSked->begin(); + } + + void setBackSked(RSkedPtr back_sked) + { + backSked = back_sked; + backSked_end.init(backSked); + backSked_end = backSked->end(); + } + void setNextStage(int stage_num) { nextStage = stage_num; } int getNextStage() { return nextStage; } @@ -426,53 +460,51 @@ /** Print Resource Schedule */ - /** @NOTE: DEBUG ONLY */ - void printSched() + void printSked() { - ThePipeline::ResSchedule tempSched; - std::cerr << "\tInst. Res. Schedule: "; - while (!resSched.empty()) { - std::cerr << '\t' << resSched.top()->stageNum << "-" - << resSched.top()->resNum << ", "; - - tempSched.push(resSched.top()); - resSched.pop(); + if (frontSked != NULL) { + frontSked->print(); } - std::cerr << std::endl; - resSched = tempSched; + if (backSked != NULL) { + backSked->print(); + } } /** Return Next Resource Stage To Be Used */ int nextResStage() { - if (resSched.empty()) - return -1; - else - return resSched.top()->stageNum; + assert((inFrontEnd && curSkedEntry != frontSked_end) || + (!inFrontEnd && curSkedEntry != backSked_end)); + + return curSkedEntry->stageNum; } /** Return Next Resource To Be Used */ int nextResource() { - if (resSched.empty()) - return -1; - else - return resSched.top()->resNum; + assert((inFrontEnd && curSkedEntry != frontSked_end) || + (!inFrontEnd && curSkedEntry != backSked_end)); + + return curSkedEntry->resNum; } - /** Remove & Deallocate a schedule entry */ - void popSchedEntry() + /** Finish using a schedule entry, increment to next entry */ + bool finishSkedEntry() { - if (!resSched.empty()) { - ScheduleEntry* sked = resSched.top(); - resSched.pop(); - if (sked != 0) { - delete sked; - - } + curSkedEntry++; + + if (inFrontEnd && curSkedEntry == frontSked_end) { + assert(backSked != NULL); + curSkedEntry.init(backSked); + curSkedEntry = backSked->begin(); + inFrontEnd = false; + } else if (!inFrontEnd && curSkedEntry == backSked_end) { + return true; } + + return false; } /** Release a Resource Request (Currently Unused) */ diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/pipeline_stage.cc --- a/src/cpu/inorder/pipeline_stage.cc Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/pipeline_stage.cc Sat Feb 12 10:14:45 2011 -0500 @@ -944,11 +944,16 @@ "completed.\n", tid, inst->seqNum, cpu->resPool->name(res_num)); - inst->popSchedEntry(); - reqs_processed++; req->stagePasses++; + + bool done_in_pipeline = inst->finishSkedEntry(); + if (done_in_pipeline) { + DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] finished " + "in pipeline.\n", tid, inst->seqNum); + break; + } } else { DPRINTF(InOrderStage, "[tid:%i]: [sn:%i] request to %s failed." "\n", tid, inst->seqNum, cpu->resPool->name(res_num)); @@ -982,7 +987,7 @@ // Activate Next Ready Thread at end of cycle DPRINTF(ThreadModel, "Attempting to activate next ready " "thread due to cache miss.\n"); - cpu->activateNextReadyContext(); + cpu->activateNextReadyContext(); } // Mark request for deletion diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/resource.cc --- a/src/cpu/inorder/resource.cc Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/resource.cc Sat Feb 12 10:14:45 2011 -0500 @@ -184,8 +184,8 @@ if (slot_num != -1) { // Get Stage # from Schedule Entry - stage_num = inst->resSched.top()->stageNum; - unsigned cmd = inst->resSched.top()->cmd; + stage_num = inst->curSkedEntry->stageNum; + unsigned cmd = inst->curSkedEntry->cmd; // Generate Resource Request inst_req = getRequest(inst, stage_num, id, slot_num, cmd); diff -r 646800970f2f -r 9c040d644df1 src/cpu/inorder/resource_pool.cc --- a/src/cpu/inorder/resource_pool.cc Sat Feb 12 10:14:43 2011 -0500 +++ b/src/cpu/inorder/resource_pool.cc Sat Feb 12 10:14:45 2011 -0500 @@ -91,6 +91,7 @@ resources.push_back(new InstBuffer("Fetch-Buffer-T1", FetchBuff2, 4, 0, _cpu, params)); + } ResourcePool::~ResourcePool() @@ -122,6 +123,16 @@ return cpu->name() + ".ResourcePool"; } +void +ResourcePool::print() _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev