I think there's a better than normal chance I introduced some bug with this code, so I'd appreciate it if people could check it out.
Gabe On 02/25/11 05:46, Gabe Black wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/502/ > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, > and Nathan Binkert. > By Gabe Black. > > > Description > > O3: Implement memory mapped IPRs for O3. > > > Diffs > > * src/cpu/o3/lsq_unit.hh (ac1bd3d1aa54) > * src/cpu/o3/lsq_unit_impl.hh (ac1bd3d1aa54) > > View Diff <http://reviews.m5sim.org/r/502/diff/> > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev
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