While trying to fix another problem, I reworked the load part of this to look more like a load satisfied by store to load forwarding than one that came back from the memory system. It didn't turn out to be necessary to fix what I was working on, but I like this version better since it's simpler and probably performs a little better.
Gabe On 02/26/11 16:31, Gabe Black wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/502/ > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, > and Nathan Binkert. > By Gabe Black. > > /Updated 2011-02-26 16:31:51.117900/ > > > Description > > O3: Implement memory mapped IPRs for O3. > > > Diffs (updated) > > * src/cpu/o3/lsq_unit.hh (ac1bd3d1aa54) > * src/cpu/o3/lsq_unit_impl.hh (ac1bd3d1aa54) > > View Diff <http://reviews.m5sim.org/r/502/diff/> > > > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev
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