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Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary ------- Mem: Fix issue with dirty block being losted when entire block transfered to non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propigate). This is required so that you can mark the cache inbetween as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues. Diffs ----- configs/common/Caches.py 9dc17725f795 src/cpu/o3/fetch_impl.hh 9dc17725f795 src/dev/io_device.cc 9dc17725f795 src/mem/cache/BaseCache.py 9dc17725f795 src/mem/cache/base.hh 9dc17725f795 src/mem/cache/base.cc 9dc17725f795 src/mem/cache/cache_impl.hh 9dc17725f795 tests/configs/inorder-timing.py 9dc17725f795 tests/configs/memtest.py 9dc17725f795 tests/configs/o3-timing-mp.py 9dc17725f795 tests/configs/o3-timing.py 9dc17725f795 tests/configs/pc-simple-atomic.py 9dc17725f795 tests/configs/pc-simple-timing.py 9dc17725f795 tests/configs/realview-simple-atomic.py 9dc17725f795 tests/configs/realview-simple-timing.py 9dc17725f795 tests/configs/simple-atomic-mp.py 9dc17725f795 tests/configs/simple-timing-mp.py 9dc17725f795 tests/configs/simple-timing.py 9dc17725f795 tests/configs/tsunami-o3-dual.py 9dc17725f795 tests/configs/tsunami-o3.py 9dc17725f795 tests/configs/tsunami-simple-atomic-dual.py 9dc17725f795 tests/configs/tsunami-simple-atomic.py 9dc17725f795 tests/configs/tsunami-simple-timing-dual.py 9dc17725f795 tests/configs/tsunami-simple-timing.py 9dc17725f795 Diff: http://reviews.m5sim.org/r/509/diff Testing ------- Thanks, Ali
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