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Ship it! Looks good to me. I didn't think about this case when originally writing the code. - Timothy On 2011-02-25 21:04:09, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/508/ > ----------------------------------------------------------- > > (Updated 2011-02-25 21:04:09) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > O3: Fix unaligned stores when cache blocked > > Without this change the a store can be issued to the cache multiple times. > If this case occurs when the l1 cache is out of mshrs (and thus blocked) > the processor will never make forward progress because each cycle it will > send a single request using the recently freed mshr and not complete the > multipart store. This will continue forever. > > > Diffs > ----- > > src/cpu/o3/lsq_unit_impl.hh 9dc17725f795 > > Diff: http://reviews.m5sim.org/r/508/diff > > > Testing > ------- > > > Thanks, > > Ali > >
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