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src/cpu/o3/bpred_unit_impl.hh <http://reviews.m5sim.org/r/570/#comment1313> The commented out code didn't work for some reason, although I agree it probably should have. As for how it worked before, you tell me.. you committed it. Somehow we got incredibly lucky and in between the instruction getting to decode, no other branches were fetched and put in the pred_hist. src/cpu/o3/bpred_unit_impl.hh <http://reviews.m5sim.org/r/570/#comment1314> Yea, we could panic here instead of asserting. - Ali On 2011-03-11 15:21:28, Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/570/ > ----------------------------------------------------------- > > (Updated 2011-03-11 15:21:28) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > ARM: Identify branches as conditional or unconditional and direct or > indirect. > > > Diffs > ----- > > src/arch/arm/insts/branch.hh 5138d1e453f1 > src/arch/arm/isa/insts/branch.isa 5138d1e453f1 > src/arch/arm/isa/templates/branch.isa 5138d1e453f1 > src/arch/arm/predecoder.hh 5138d1e453f1 > src/arch/arm/types.hh 5138d1e453f1 > src/cpu/o3/bpred_unit_impl.hh 5138d1e453f1 > > Diff: http://reviews.m5sim.org/r/570/diff > > > Testing > ------- > > > Thanks, > > Ali > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
