Reviewboard is complaining about posting consecutive changesets to the board for some reason. When I view the diff it gives an error message about not being able to apply the patch. So for now, I just posted both patches merged and will split on commit.
Anyone else run into this problem? On Mon, Mar 14, 2011 at 8:34 PM, Korey Sewell <[email protected]> wrote: > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/578/ > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > By Korey Sewell. > > *Updated 2011-03-14 17:34:17.189549* > Description (updated) > > isa: get rid of expandForMT function > MIPS is the only ISA that cares about having a piece of ISA state integrate > multiple threads so add constants for MIPS and relieve the other ISAs from > having > to define this. Also, InOrder was the only core that was actively calling > this function > * * * > isa: get rid of corespecific type > The CoreSpecific type was used as a proxy to pass in HW specific params to > a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense > to not force every other ISA to use CoreSpecific as well use a special > reset function to set it. That probably should go in a PowerOn reset fault > anyway. > > Diffs (updated) > > - src/arch/alpha/isa.hh (6c9b532da0a6) > - src/arch/alpha/types.hh (6c9b532da0a6) > - src/arch/arm/types.hh (6c9b532da0a6) > - src/arch/mips/isa.hh (6c9b532da0a6) > - src/arch/mips/isa.cc (6c9b532da0a6) > - src/arch/power/types.hh (6c9b532da0a6) > - src/arch/sparc/types.hh (6c9b532da0a6) > - src/arch/x86/types.hh (6c9b532da0a6) > - src/cpu/BaseCPU.py (6c9b532da0a6) > - src/cpu/base.hh (6c9b532da0a6) > - src/cpu/inorder/cpu.hh (6c9b532da0a6) > - src/cpu/inorder/cpu.cc (6c9b532da0a6) > > View Diff <http://reviews.m5sim.org/r/578/diff/> > -- - Korey _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
