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There are a number of style issues to clean up, but otherwise this seems mostly ok. I'm still not crazy about having an mt.hh that's only used in InOrder and MIPS, as far as I'm aware. That's ISA specific behavior masquerading as something generic, but that's probably a separate issue from this change. src/arch/sparc/isa/decoder.isa <http://reviews.m5sim.org/r/583/#comment1349> Needs a space between the comma and None. Should this be marked as IsUncondControl as well? src/arch/sparc/isa/formats/mem/basicmem.isa <http://reviews.m5sim.org/r/583/#comment1350> You shouldn't add this. This isn't really a C++ file anyway. src/arch/sparc/isa/formats/mem/swap.isa <http://reviews.m5sim.org/r/583/#comment1351> This line is too long. It needs to be split up. Better yet, exec_output should be appended before the return. src/arch/sparc/isa/formats/mem/util.isa <http://reviews.m5sim.org/r/583/#comment1352> Checking for faults here (for SPARC at least) isn't necessary as far as I remember. src/arch/sparc/isa/formats/mem/util.isa <http://reviews.m5sim.org/r/583/#comment1353> Checking for a fault here is probably also unnecessary. src/arch/sparc/mt.hh <http://reviews.m5sim.org/r/583/#comment1345> Some of these header files don't need to be included. src/arch/sparc/mt.hh <http://reviews.m5sim.org/r/583/#comment1346> Never put "using namespace" in a header file. src/arch/sparc/mt.hh <http://reviews.m5sim.org/r/583/#comment1347> This isn't really a user configuration problem since there's no way to even request multithreaded behavior like this in SPARC. I think these should be panics. src/arch/sparc/registers.hh <http://reviews.m5sim.org/r/583/#comment1348> This seems redundant. Can't the CPU model add them up just as easily? - Gabe On 2011-03-14 17:39:33, Korey Sewell wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/583/ > ----------------------------------------------------------- > > (Updated 2011-03-14 17:39:33) > > > Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and > Nathan Binkert. > > > Summary > ------- > > sparc: compilation fixes for inorder > Add a few constants and functions that the InOrder model wants for SPARC. > * * * > sparc: add eaComp function > InOrder separates the address generation from the actual access so give > Sparc that functionality > * * * > sparc: add control flags for branches > branch predictors and other cpu model functions need to know specific > information > about branches, so add the necessary flags here > > > Diffs > ----- > > src/arch/sparc/isa/decoder.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/branch.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/mem/basicmem.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/mem/swap.isa 6c9b532da0a6 > src/arch/sparc/isa/formats/mem/util.isa 6c9b532da0a6 > src/arch/sparc/mt.hh PRE-CREATION > src/arch/sparc/registers.hh 6c9b532da0a6 > src/cpu/inorder/cpu.cc 6c9b532da0a6 > src/cpu/inorder/inorder_dyn_inst.cc 6c9b532da0a6 > > Diff: http://reviews.m5sim.org/r/583/diff > > > Testing > ------- > > > Thanks, > > Korey > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
