changeset bb2d04f0b8fb in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=bb2d04f0b8fb
description:
O3: Update regressions for mem block caching change.
diffstat:
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini | 18 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 1732
+++++-----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini | 16 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 934
++--
6 files changed, 1367 insertions(+), 1357 deletions(-)
diffs (truncated from 3678 to 300 lines):
diff -r b01a51ff05fa -r bb2d04f0b8fb
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Thu Mar 17 19:20:19 2011 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Thu Mar 17 19:20:19 2011 -0500
@@ -10,12 +10,12 @@
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus
physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+console=/chips/pd/randd/dist/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/chips/pd/randd/dist/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/chips/pd/randd/dist/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
@@ -142,6 +142,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -440,6 +441,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -573,6 +575,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -871,6 +874,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=4
@@ -922,7 +926,7 @@
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -942,7 +946,7 @@
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
@@ -967,6 +971,7 @@
block_size=64
forward_snoops=false
hash_delay=1
+is_top_level=true
latency=50000
max_miss_count=0
mshrs=20
@@ -998,6 +1003,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=10000
max_miss_count=0
mshrs=92
@@ -1068,7 +1074,7 @@
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/chips/pd/randd/dist/disks/linux-latest.img
read_only=true
[system.terminal]
diff -r b01a51ff05fa -r bb2d04f0b8fb
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Thu Mar
17 19:20:19 2011 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Thu Mar
17 19:20:19 2011 -0500
@@ -5,13 +5,13 @@
All Rights Reserved
-M5 compiled Feb 7 2011 01:46:17
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:46:32
-M5 executing on burrito
+M5 compiled Mar 15 2011 18:10:57
+M5 revision ee89694ad8dc 8081 default
ext/mem_block_transfer_O3_regressions.patch tip qtip
+M5 started Mar 15 2011 18:10:59
+M5 executing on u200439-lin.austin.arm.com
command line: build/ALPHA_FS/m5.fast -d
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re
tests/run.py
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 118370500
-Exiting @ tick 1900831034500 because m5_exit instruction encountered
+Exiting @ tick 1900831106500 because m5_exit instruction encountered
diff -r b01a51ff05fa -r bb2d04f0b8fb
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Thu Mar 17 19:20:19 2011 -0500
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Thu Mar 17 19:20:19 2011 -0500
@@ -1,395 +1,395 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 67358 #
Simulator instruction rate (inst/s)
-host_mem_usage 313516 #
Number of bytes of host memory used
-host_seconds 846.09 #
Real time elapsed on the host
-host_tick_rate 2246601111 #
Simulator tick rate (ticks/s)
+host_inst_rate 185731 #
Simulator instruction rate (inst/s)
+host_mem_usage 330796 #
Number of bytes of host memory used
+host_seconds 306.85 #
Real time elapsed on the host
+host_tick_rate 6194726969 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 56990797 #
Number of instructions simulated
+sim_insts 56990828 #
Number of instructions simulated
sim_seconds 1.900831 #
Number of seconds simulated
-sim_ticks 1900831034500 #
Number of ticks simulated
+sim_ticks 1900831106500 #
Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits 5875698 #
Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 11164328 #
Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect 27744 #
Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect 509294 #
Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 10430748 #
Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 12489171 #
Number of BP lookups
-system.cpu0.BPredUnit.usedRAS 879952 #
Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches 7522146 #
Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 923087 #
number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits 5875746 #
Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups 11164335 #
Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect 27734 #
Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect 509345 #
Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted 10431005 #
Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 12489231 #
Number of BP lookups
+system.cpu0.BPredUnit.usedRAS 879926 #
Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches 7522155 #
Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 922955 #
number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 78252168
# Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 0.636069
# Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 1.403085
# Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 78251630
# Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 0.636074
# Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 1.403101
# Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 56997236 72.84%
72.84% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 9310198 11.90%
84.74% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 5423748 6.93%
91.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 2443659 3.12%
94.79% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 1857092 2.37%
97.16% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5 632524 0.81%
97.97% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6 342942 0.44%
98.41% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7 321682 0.41%
98.82% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8 923087 1.18%
100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 56997001 72.84%
72.84% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 9309948 11.90%
84.74% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 5423861 6.93%
91.67% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 2443172 3.12%
94.79% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 1857246 2.37%
97.16% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5 632479 0.81%
97.97% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6 343172 0.44%
98.41% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7 321796 0.41%
98.82% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8 922955 1.18%
100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 78252168
# Number of insts commited each cycle
-system.cpu0.commit.COM:count 49773781 #
Number of instructions committed
+system.cpu0.commit.COM:committed_per_cycle::total 78251630
# Number of insts commited each cycle
+system.cpu0.commit.COM:count 49773809 #
Number of instructions committed
system.cpu0.commit.COM:fp_insts 245595 #
Number of committed floating point instructions.
-system.cpu0.commit.COM:function_calls 636046 #
Number of function calls committed.
-system.cpu0.commit.COM:int_insts 46098576 #
Number of committed integer instructions.
-system.cpu0.commit.COM:loads 7894849 #
Number of loads committed
+system.cpu0.commit.COM:function_calls 636047 #
Number of function calls committed.
+system.cpu0.commit.COM:int_insts 46098602 #
Number of committed integer instructions.
+system.cpu0.commit.COM:loads 7894859 #
Number of loads committed
system.cpu0.commit.COM:membars 191655 #
Number of memory barriers committed
-system.cpu0.commit.COM:refs 13318728 #
Number of memory references committed
+system.cpu0.commit.COM:refs 13318738 #
Number of memory references committed
system.cpu0.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 652792 #
The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 49773781 #
The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls 564764 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 7279166 #
The number of squashed insts skipped by commit
-system.cpu0.committedInsts 46913211 #
Number of Instructions Simulated
-system.cpu0.committedInsts_total 46913211 #
Number of Instructions Simulated
-system.cpu0.cpi 2.403631 #
CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.403631 #
CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0 178258
# number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 178258
# number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14381.476316
# average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts 652841 #
The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 49773809 #
The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls 564763 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts 7279602 #
The number of squashed insts skipped by commit
+system.cpu0.committedInsts 46913237 #
Number of Instructions Simulated
+system.cpu0.committedInsts_total 46913237 #
Number of Instructions Simulated
+system.cpu0.cpi 2.403611 #
CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.403611 #
CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0 178261
# number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 178261
# number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14383.272201
# average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf
# average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf
# average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10558.033333
# average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0 158899 #
number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 158899
# number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 278411000
# number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108601
# miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0 19359
# number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 19359
# number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits 4359
# number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158370500
# number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084148
# mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10560.425277
# average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0 158904 #
number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 158904
# number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 278417000
# number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108588
# miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0 19357
# number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 19357
# number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits 4355
# number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158427500
# number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084157
# mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf
# mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf
# mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 15000
# number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0 8018067 #
number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8018067
# number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 23754.598189
# average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses 15002
# number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0 8017759 #
number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8017759
# number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 23757.902186
# average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf
# average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf
# average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.786651
# average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.503104
# average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf
# average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0 6640677 #
number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 6640677 #
number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 32719346000 #
number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0 0.171786 #
miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0 1377390 #
number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1377390 #
number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 392262 #
number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 23413327000
# number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122864
# mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0 6640640 #
number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6640640 #
number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 32717458500 #
number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0 0.171759 #
miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0 1377119 #
number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1377119 #
number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 391971 #
number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 23413523000
# number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122871
# mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf
# mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf
# mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 985128 #
number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920863000
# number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_misses 985148 #
number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920844000
# number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.StoreCondReq_accesses::0 185114
# number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 185114
# number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13329.315068
# average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13326.438356
# average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf
# average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf
# average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10326.164384
# average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10323.150685
# average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_hits::0 181464 #
number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 181464
# number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 48652000
# number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency 48641500
# number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019718
# miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_misses::0 3650 #
number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 3650
# number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37690500
# number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37679500
# number of StoreCondReq MSHR miss cycles
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