changeset afcb66f4b964 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=afcb66f4b964
description:
ARM: Previous change didn't end up setting instFlags, this does.
diffstat:
src/arch/arm/isa/insts/str.isa | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diffs (38 lines):
diff -r bb2d04f0b8fb -r afcb66f4b964 src/arch/arm/isa/insts/str.isa
--- a/src/arch/arm/isa/insts/str.isa Thu Mar 17 19:20:19 2011 -0500
+++ b/src/arch/arm/isa/insts/str.isa Thu Mar 17 19:20:19 2011 -0500
@@ -222,7 +222,6 @@
decConstBase = 'StoreExImm'
basePrefix = 'MemoryExImm'
nameFunc = staticmethod(storeImmClassName)
- instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreImmEx, self).__init__(*args, **kargs)
@@ -302,7 +301,6 @@
decConstBase = 'StoreExDImm'
basePrefix = 'MemoryExDImm'
nameFunc = staticmethod(storeDoubleImmClassName)
- instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreDoubleImmEx, self).__init__(*args, **kargs)
@@ -370,10 +368,14 @@
buildDoubleStores("strd")
- StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
- StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
- StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
- StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
+ StoreImmEx("strex", False, True, False, size=4, flavor="exclusive",
+ instFlags = ['IsStoreConditional']).emit()
+ StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive",
+ instFlags = ['IsStoreConditional']).emit()
+ StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive",
+ instFlags = ['IsStoreConditional']).emit()
+ StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive",
+ instFlags = ['IsStoreConditional']).emit()
StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
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