----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/611/#review1082 -----------------------------------------------------------
This looks great, I just have a few minor suggestions below. It seems like the next step is to figure out how to deal with functional accesses not succeeding in the CPUs and devices. src/mem/ruby/system/RubyPort.cc <http://reviews.m5sim.org/r/611/#comment1438> Please add comments to this function explaining what is going on here. src/mem/ruby/system/RubyPort.cc <http://reviews.m5sim.org/r/611/#comment1439> It seems that the ro and rw counter checks should happen here, before doing any functional accesses. src/mem/ruby/system/RubyPort.cc <http://reviews.m5sim.org/r/611/#comment1440> Try to avoid the duplicate code between here... src/mem/ruby/system/RubyPort.cc <http://reviews.m5sim.org/r/611/#comment1441> ...and here. src/mem/ruby/system/RubyPort.cc <http://reviews.m5sim.org/r/611/#comment1442> Are functional packets put on the stack or the heap? I seem to remember the former, but I could be wrong. - Brad On 2011-03-31 20:44:17, Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.m5sim.org/r/611/ > ----------------------------------------------------------- > > (Updated 2011-03-31 20:44:17) > > > Review request for Default. > > > Summary > ------- > > Ruby: Add support for functional accesses > This patch is meant for aiding discussions on implementation of functional > access support in Ruby. > > > Diffs > ----- > > configs/ruby/MESI_CMP_directory.py c7302d55d644 > configs/ruby/Ruby.py c7302d55d644 > src/mem/ruby/network/Network.cc c7302d55d644 > src/mem/ruby/network/Network.py c7302d55d644 > src/mem/ruby/profiler/Profiler.cc c7302d55d644 > src/mem/ruby/profiler/Profiler.py c7302d55d644 > src/mem/ruby/recorder/Tracer.cc c7302d55d644 > src/mem/ruby/recorder/Tracer.py c7302d55d644 > src/mem/ruby/system/AbstractMemory.hh PRE-CREATION > src/mem/ruby/system/AbstractMemory.cc PRE-CREATION > src/mem/ruby/system/Cache.py c7302d55d644 > src/mem/ruby/system/CacheMemory.hh c7302d55d644 > src/mem/ruby/system/CacheMemory.cc c7302d55d644 > src/mem/ruby/system/DirectoryMemory.hh c7302d55d644 > src/mem/ruby/system/DirectoryMemory.cc c7302d55d644 > src/mem/ruby/system/DirectoryMemory.py c7302d55d644 > src/mem/ruby/system/RubyPort.hh c7302d55d644 > src/mem/ruby/system/RubyPort.cc c7302d55d644 > src/mem/ruby/system/RubySystem.py c7302d55d644 > src/mem/ruby/system/SConscript c7302d55d644 > src/mem/ruby/system/Sequencer.cc c7302d55d644 > src/mem/ruby/system/Sequencer.py c7302d55d644 > src/mem/ruby/system/System.hh c7302d55d644 > src/mem/ruby/system/System.cc c7302d55d644 > > Diff: http://reviews.m5sim.org/r/611/diff > > > Testing > ------- > > > Thanks, > > Nilay > > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
