Thanks for pointing this out. The hammer protocol included a optimization for uniprocessor DMA that was probably was just too aggressive to be worth the complexity. The optimization broke when I fixed another DMA bug in the protocol last week, but I failed realize that since I offend don't think about uniprocessor scenarios. Rather than try to revive the optimization, I'm just going to remove it.
Patch is forthcoming. Brad > -----Original Message----- > From: [email protected] [mailto:[email protected]] > On Behalf Of Lisa Hsu > Sent: Thursday, March 31, 2011 5:39 PM > To: M5 Developer List > Subject: [m5-dev] ruby_mem_tester.py > > Hi all, > > As I prepared to push a bunch of stuff today I found that the following > command line fails at the head of the the clean tree: > > ALPHA_SE_MOESI_hammer/m5.debug configs/example/ruby_mem_test.py > -l 1000 --num-dma 2 > > I pushed my changes anyway because they didn't make any difference on > this error, but I've never run ruby_mem_test before, haven't worked with > DMA sequencers, and am not particularly cozy with MOESI_hammer, and > was wondering if this was known or unknown, expected or unexpected. I > presume unknown and unexpected. > > The error is an invalid transition from MI with event Writeback_Nack. It > seems to occur anytime --num-dma > 1. Is this a big concern? Should I add > this to flyspray? > > Lisa > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
