changeset 89221928d131 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=89221928d131
description:
CPU: Remove references to memory copy operations
diffstat:
src/cpu/base_dyn_inst.hh | 7 -------
src/cpu/inorder/inorder_dyn_inst.hh | 1 -
src/cpu/o3/commit_impl.hh | 3 ---
src/cpu/ozone/lw_back_end_impl.hh | 3 ---
src/cpu/static_inst.hh | 2 --
src/cpu/thread_state.hh | 12 ------------
6 files changed, 0 insertions(+), 28 deletions(-)
diffs (102 lines):
diff -r 5806937a7c67 -r 89221928d131 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Mon Apr 04 11:42:25 2011 -0500
+++ b/src/cpu/base_dyn_inst.hh Mon Apr 04 11:42:26 2011 -0500
@@ -252,12 +252,6 @@
/** The effective physical address. */
Addr physEffAddr;
- /** Effective virtual address for a copy source. */
- Addr copySrcEffAddr;
-
- /** Effective physical address for a copy source. */
- Addr copySrcPhysEffAddr;
-
/** The memory request flags (from translation). */
unsigned memReqFlags;
@@ -499,7 +493,6 @@
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
- bool isCopy() const { return staticInst->isCopy(); }
bool isInteger() const { return staticInst->isInteger(); }
bool isFloating() const { return staticInst->isFloating(); }
bool isControl() const { return staticInst->isControl(); }
diff -r 5806937a7c67 -r 89221928d131 src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh Mon Apr 04 11:42:25 2011 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.hh Mon Apr 04 11:42:26 2011 -0500
@@ -350,7 +350,6 @@
{ return staticInst->isStoreConditional(); }
bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
- bool isCopy() const { return staticInst->isCopy(); }
bool isInteger() const { return staticInst->isInteger(); }
bool isFloating() const { return staticInst->isFloating(); }
bool isControl() const { return staticInst->isControl(); }
diff -r 5806937a7c67 -r 89221928d131 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Mon Apr 04 11:42:25 2011 -0500
+++ b/src/cpu/o3/commit_impl.hh Mon Apr 04 11:42:26 2011 -0500
@@ -1199,9 +1199,6 @@
head_inst->renamedDestRegIdx(i));
}
- if (head_inst->isCopy())
- panic("Should not commit any copy instructions!");
-
// Finally clear the head ROB entry.
rob->retireHead(tid);
diff -r 5806937a7c67 -r 89221928d131 src/cpu/ozone/lw_back_end_impl.hh
--- a/src/cpu/ozone/lw_back_end_impl.hh Mon Apr 04 11:42:25 2011 -0500
+++ b/src/cpu/ozone/lw_back_end_impl.hh Mon Apr 04 11:42:26 2011 -0500
@@ -1205,9 +1205,6 @@
inst->traceData = NULL;
}
- if (inst->isCopy())
- panic("Should not commit any copy instructions!");
-
inst->clearDependents();
frontEnd->addFreeRegs(freed_regs);
diff -r 5806937a7c67 -r 89221928d131 src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh Mon Apr 04 11:42:25 2011 -0500
+++ b/src/cpu/static_inst.hh Mon Apr 04 11:42:26 2011 -0500
@@ -117,7 +117,6 @@
IsIndexed, ///< Accesses memory with an indexed address
computation
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
- IsCopy, ///< Fast Cache block copy
IsControl, ///< Control transfer instruction.
IsDirectControl, ///< PC relative control transfer.
@@ -228,7 +227,6 @@
bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
bool isPrefetch() const { return isInstPrefetch() ||
isDataPrefetch(); }
- bool isCopy() const { return flags[IsCopy];}
bool isInteger() const { return flags[IsInteger]; }
bool isFloating() const { return flags[IsFloating]; }
diff -r 5806937a7c67 -r 89221928d131 src/cpu/thread_state.hh
--- a/src/cpu/thread_state.hh Mon Apr 04 11:42:25 2011 -0500
+++ b/src/cpu/thread_state.hh Mon Apr 04 11:42:26 2011 -0500
@@ -200,18 +200,6 @@
#endif
public:
- /**
- * Temporary storage to pass the source address from copy_load to
- * copy_store.
- * @todo Remove this temporary when we have a better way to do it.
- */
- Addr copySrcAddr;
- /**
- * Temp storage for the physical source address of a copy.
- * @todo Remove this temporary when we have a better way to do it.
- */
- Addr copySrcPhysAddr;
-
/*
* number of executed instructions, for matching with syscall trace
* points in EIO files.
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
