changeset 5806937a7c67 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5806937a7c67
description:
O3: Update stats for memory order violation checking patch.
diffstat:
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout |
9 +-
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt |
752 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt |
772 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini |
3 +
tests/long/00.gzip/ref/sparc/linux/o3-timing/simout |
9 +-
tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt |
739 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini |
3 +
tests/long/00.gzip/ref/x86/linux/o3-timing/simout |
8 +-
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt |
724 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout |
13 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt |
2288 ++++----
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini |
12 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout |
11 +-
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt |
1121 ++--
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini |
4 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr |
2 -
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout |
11 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt |
1046 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status |
2 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal |
0
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini |
4 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt |
756 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini |
5 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/simout |
11 +-
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt |
734 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini |
4 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt |
794 +-
tests/long/20.parser/ref/x86/linux/o3-timing/config.ini |
5 +-
tests/long/20.parser/ref/x86/linux/o3-timing/simout |
8 +-
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt |
774 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/30.eon/ref/alpha/tru64/o3-timing/simout |
11 +-
tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt |
740 +-
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout |
11 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt |
767 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout |
9 +-
tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt |
700 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt |
780 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout |
9 +-
tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt |
776 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt |
801 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout |
9 +-
tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt |
752 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt |
786 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout |
11 +-
tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt |
724 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout |
9 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt |
758 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini |
5 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/simout |
11 +-
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt |
714 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini |
3 +
tests/quick/00.hello/ref/alpha/linux/o3-timing/simout |
9 +-
tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt |
592 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini |
3 +
tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout |
9 +-
tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt |
590 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini |
2 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/simout |
9 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt |
508 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini |
3 +
tests/quick/00.hello/ref/mips/linux/o3-timing/simout |
9 +-
tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt |
559 +-
tests/quick/00.hello/ref/power/linux/o3-timing/config.ini |
3 +
tests/quick/00.hello/ref/power/linux/o3-timing/simerr |
2 +-
tests/quick/00.hello/ref/power/linux/o3-timing/simout |
9 +-
tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt |
610 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini |
3 +
tests/quick/00.hello/ref/x86/linux/o3-timing/simout |
11 +-
tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt |
562 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini |
3 +
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout |
9 +-
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt |
928 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini |
3 +
tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout |
9 +-
tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt |
452 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini |
9 +
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout |
69 +-
tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt |
2626 +++++-----
97 files changed, 13375 insertions(+), 13332 deletions(-)
diffs (truncated from 32938 to 300 lines):
diff -r 3d6c08c877a9 -r 5806937a7c67
tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Mon Apr 04
11:42:23 2011 -0500
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Mon Apr 04
11:42:25 2011 -0500
@@ -115,6 +115,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@@ -413,6 +414,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
@@ -448,6 +450,7 @@
block_size=64
forward_snoops=true
hash_delay=1
+is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
diff -r 3d6c08c877a9 -r 5806937a7c67
tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Apr 04
11:42:23 2011 -0500
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Mon Apr 04
11:42:25 2011 -0500
@@ -5,10 +5,9 @@
All Rights Reserved
-M5 compiled Feb 7 2011 01:47:18
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:47:50
-M5 executing on burrito
+M5 compiled Mar 17 2011 21:44:37
+M5 started Mar 17 2011 22:44:08
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.fast -d
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py
build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
@@ -44,4 +43,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 162779779500 because target called exit()
+Exiting @ tick 162342217500 because target called exit()
diff -r 3d6c08c877a9 -r 5806937a7c67
tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Apr 04
11:42:23 2011 -0500
+++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Mon Apr 04
11:42:25 2011 -0500
@@ -1,41 +1,41 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 121046 #
Simulator instruction rate (inst/s)
-host_mem_usage 226784 #
Number of bytes of host memory used
-host_seconds 4672.20 #
Real time elapsed on the host
-host_tick_rate 34840083 #
Simulator tick rate (ticks/s)
+host_inst_rate 243015 #
Simulator instruction rate (inst/s)
+host_mem_usage 208616 #
Number of bytes of host memory used
+host_seconds 2327.23 #
Real time elapsed on the host
+host_tick_rate 69757618 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 565552443 #
Number of instructions simulated
-sim_seconds 0.162780 #
Number of seconds simulated
-sim_ticks 162779779500 #
Number of ticks simulated
+sim_seconds 0.162342 #
Number of seconds simulated
+sim_ticks 162342217500 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 63926991 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 71320793 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 193 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 4120736 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 70355271 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 76295210 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1675650 #
Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 63645886 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 71175082 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 199 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 4119052 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 70244988 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 76158972 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1672188 #
Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 19927815 #
number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 20370282 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 315794082
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.905853
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.338192
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 315015358
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.910564
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.344745
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 102454006 32.44%
32.44% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 100543040 31.84%
64.28% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 36844526 11.67%
75.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 9307171 2.95%
78.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 10247874 3.25%
82.14% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 21736977 6.88%
89.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 12524254 3.97%
92.99% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 2208419 0.70%
93.69% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 19927815 6.31%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 102187516 32.44%
32.44% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 100337503 31.85%
64.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 36333939 11.53%
75.82% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 9834278 3.12%
78.95% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 9585018 3.04%
81.99% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 21675104 6.88%
88.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 13171126 4.18%
93.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1520592 0.48%
93.53% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 20370282 6.47%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 315794082
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 315015358
# Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 #
Number of instructions committed
system.cpu.commit.COM:fp_insts 1520 #
Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 1197610 #
Number of function calls committed.
@@ -44,352 +44,352 @@
system.cpu.commit.COM:membars 0 #
Number of memory barriers committed
system.cpu.commit.COM:refs 153965363 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4119890 #
The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 4118243 #
The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 #
The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 60520337 #
The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 59876142 #
The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 #
Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 #
Number of Instructions Simulated
-system.cpu.cpi 0.575649 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.575649 #
CPI: Total CPI of All Threads
+system.cpu.cpi 0.574101 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.574101 #
CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 #
number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 3 #
number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 112312480 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 15160.742892
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7367.811163
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 111525313 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 11934036500 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007009 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 787167 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 569138 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1606396500
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001941 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 218029 #
number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 112204531 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 15171.487288
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7363.877609
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 111416977 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11948365500 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007019 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 787554 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 569368 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1606695000
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001945 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 218186 #
number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14279.189894
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11300.460826
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 38165820 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 18355912888 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.032584 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1285501 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1028584 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2903280494
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 256917 #
number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.150943
# average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 14289.032218
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11301.125107
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 38165226 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 18377052890 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.032600 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1286095 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1029147 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2903801494
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006513 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 256948 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 7344.320755
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 315.175064 #
Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 314.821095 #
Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 106 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 773498
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 778498
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 224000
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 151763801 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 14613.989982 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9495.136277
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 149691133 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 30289949388 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.013657 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 2072668 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1597722 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4509676994
# number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003130 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 474946 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 151655852 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 14624.181040 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9493.104038
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 149582203 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 30325418390 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.013673 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 2073649 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1598515 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4510496494
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003133 #
mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 475134 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999550 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.156298 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 151763801 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 14613.989982
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9495.136277
# average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999549 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.151824 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 151655852 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 14624.181040
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9493.104038
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 149691133 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 30289949388 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.013657 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 2072668 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 1597722 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4509676994
# number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003130 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 474946 #
number of overall MSHR misses
+system.cpu.dcache.overall_hits 149582203 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 30325418390 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.013673 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 2073649 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 1598515 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4510496494
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003133 #
mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 475134 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 470850 #
number of replacements
-system.cpu.dcache.sampled_refs 474946 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 471038 #
number of replacements
+system.cpu.dcache.sampled_refs 475134 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.156298 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 149691136 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126698000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 423042 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 45000094 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 877 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 4176202 #
Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 688674202 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 142513181 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 122905016 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 9698747 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 3338 #
Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 5375791 #
Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 163053496 #
DTB accesses
+system.cpu.dcache.tagsinuse 4094.151824 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 149582206 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126677000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 423176 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 44833716 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 844 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4163323 #
Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 687863087 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 142213399 #
Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 122593858 #
Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 9601978 #
Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 3402 #
Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 5374385 #
Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 163150258 #
DTB accesses
system.cpu.dtb.data_acv 0 #
DTB access violations
-system.cpu.dtb.data_hits 163001268 #
DTB hits
-system.cpu.dtb.data_misses 52228 #
DTB misses
+system.cpu.dtb.data_hits 163097305 #
DTB hits
+system.cpu.dtb.data_misses 52953 #
DTB misses
system.cpu.dtb.fetch_accesses 0 #
ITB accesses
system.cpu.dtb.fetch_acv 0 #
ITB acv
system.cpu.dtb.fetch_hits 0 #
ITB hits
system.cpu.dtb.fetch_misses 0 #
ITB misses
-system.cpu.dtb.read_accesses 122206073 #
DTB read accesses
+system.cpu.dtb.read_accesses 122245622 #
DTB read accesses
system.cpu.dtb.read_acv 0 #
DTB read access violations
-system.cpu.dtb.read_hits 122181392 #
DTB read hits
-system.cpu.dtb.read_misses 24681 #
DTB read misses
-system.cpu.dtb.write_accesses 40847423 #
DTB write accesses
+system.cpu.dtb.read_hits 122220880 #
DTB read hits
+system.cpu.dtb.read_misses 24742 #
DTB read misses
+system.cpu.dtb.write_accesses 40904636 #
DTB write accesses
system.cpu.dtb.write_acv 0 #
DTB write access violations
_______________________________________________
m5-dev mailing list
m5-dev@m5sim.org
http://m5sim.org/mailman/listinfo/m5-dev
