changeset 20362a3a1540 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=20362a3a1540
description:
ARM: Update stats for previous changes.
diffstat:
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
| 708 +++---
tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/simerr
| 4 -
tests/long/00.gzip/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 6 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 2 +
tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout
| 12 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1044 ++++-----
tests/long/10.linux-boot/ref/arm/linux/realview-o3/status
| 2 +-
tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
| 4 +
tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini
| 8 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out
| 999 +++++++++
tests/long/10.mcf/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt
| 771 +++---
tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
| 4 +
tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out
| 999 +++++++++
tests/long/10.mcf/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
| 4 +
tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out
| 999 +++++++++
tests/long/10.mcf/ref/arm/linux/simple-timing/simerr
| 4 -
tests/long/10.mcf/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/20.parser/ref/arm/linux/o3-timing/config.ini
| 8 +-
tests/long/20.parser/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt
| 800 +++---
tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/20.parser/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/20.parser/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/20.parser/ref/arm/linux/simple-timing/simerr
| 2 -
tests/long/20.parser/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/30.eon/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/30.eon/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt
| 732 +++---
tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/30.eon/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/30.eon/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/30.eon/ref/arm/linux/simple-timing/simerr
| 10 +-
tests/long/30.eon/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 792 +++---
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr
| 6 -
tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out
| 258 ++
tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt
| 800 +++---
tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/50.vortex/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out
| 258 ++
tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/simerr
| 8 -
tests/long/50.vortex/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out
| 258 ++
tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt
| 734 +++---
tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr
| 2 -
tests/long/60.bzip2/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini
| 6 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/simout
| 10 +-
tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out
| 276 ++
tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt
| 732 +++---
tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini
| 2 +-
tests/long/70.twolf/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out
| 276 ++
tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt
| 14 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini
| 2 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/simerr
| 10 -
tests/long/70.twolf/ref/arm/linux/simple-timing/simout
| 7 +-
tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out
| 276 ++
tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt
| 14 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini
| 4 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/simout
| 10 +-
tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt
| 658 +++---
tests/quick/00.hello/ref/arm/linux/simple-atomic/simout
| 7 +-
tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt
| 8 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/simout
| 7 +-
tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt
| 10 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 7 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 20 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
| 6 -
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 9 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 520 ++--
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status
| 2 +-
tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
113 files changed, 9072 insertions(+), 4490 deletions(-)
diffs (truncated from 16359 to 300 lines):
diff -r 9e3f7f00fa90 -r 20362a3a1540
tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Mon Apr 04
11:42:29 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini Mon Apr 04
11:42:31 2011 -0500
@@ -25,6 +25,8 @@
BTBTagSize=16
LFSTSize=1024
LQEntries=32
+LSQCheckLoads=true
+LSQDepCheckShift=4
RASSize=16
SQEntries=32
SSITSize=1024
@@ -491,12 +493,12 @@
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/chips/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
diff -r 9e3f7f00fa90 -r 20362a3a1540
tests/long/00.gzip/ref/arm/linux/o3-timing/simout
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Mon Apr 04 11:42:29
2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/simout Mon Apr 04 11:42:31
2011 -0500
@@ -5,10 +5,10 @@
All Rights Reserved
-M5 compiled Mar 18 2011 20:12:03
-M5 started Mar 18 2011 21:36:19
-M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+M5 compiled Mar 30 2011 17:47:57
+M5 started Mar 30 2011 17:54:33
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py
build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
@@ -42,4 +42,4 @@
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 196536810500 because target called exit()
+Exiting @ tick 196513140500 because target called exit()
diff -r 9e3f7f00fa90 -r 20362a3a1540
tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt
--- a/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Mon Apr 04
11:42:29 2011 -0500
+++ b/tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt Mon Apr 04
11:42:31 2011 -0500
@@ -1,142 +1,142 @@
---------- Begin Simulation Statistics ----------
-host_inst_rate 157384 #
Simulator instruction rate (inst/s)
-host_mem_usage 221236 #
Number of bytes of host memory used
-host_seconds 3827.32 #
Real time elapsed on the host
-host_tick_rate 51350965 #
Simulator tick rate (ticks/s)
+host_inst_rate 79580 #
Simulator instruction rate (inst/s)
+host_mem_usage 255900 #
Number of bytes of host memory used
+host_seconds 7569.27 #
Real time elapsed on the host
+host_tick_rate 25961971 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 602359870 #
Number of instructions simulated
-sim_seconds 0.196537 #
Number of seconds simulated
-sim_ticks 196536810500 #
Number of ticks simulated
+sim_insts 602359865 #
Number of instructions simulated
+sim_seconds 0.196513 #
Number of seconds simulated
+sim_ticks 196513140500 #
Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 75961485 #
Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 82107435 #
Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 1596 #
Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 3833895 #
Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 81873360 #
Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 88392158 #
Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1389747 #
Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches 70826856 #
Number of branches committed
-system.cpu.commit.COM:bw_lim_events 7927801 #
number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 75744427 #
Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 81879675 #
Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 1640 #
Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 3832102 #
Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 81880205 #
Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 88398894 #
Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1393010 #
Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 70828614 #
Number of branches committed
+system.cpu.commit.COM:bw_lim_events 7897771 #
number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 379302454
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.588073
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.904864
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 379244728
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.588315
# Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.904338
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00%
0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 123535993 32.57%
32.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 123034003 32.44%
65.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 59238565 15.62%
80.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 18407109 4.85%
85.48% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 17194886 4.53%
90.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 14352047 3.78%
93.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 7619076 2.01%
95.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 7992974 2.11%
97.91% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 7927801 2.09%
100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 123478650 32.56%
32.56% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 123013107 32.44%
65.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 59170888 15.60%
80.60% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 18488020 4.87%
85.47% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 17225820 4.54%
90.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 14373715 3.79%
93.80% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 7590349 2.00%
95.81% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 8006408 2.11%
97.92% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 7897771 2.08%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00%
100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0
# Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8
# Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 379302454
# Number of insts commited each cycle
-system.cpu.commit.COM:count 602359921 #
Number of instructions committed
+system.cpu.commit.COM:committed_per_cycle::total 379244728
# Number of insts commited each cycle
+system.cpu.commit.COM:count 602359916 #
Number of instructions committed
system.cpu.commit.COM:fp_insts 16 #
Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 997573 #
Number of function calls committed.
-system.cpu.commit.COM:int_insts 533522695 #
Number of committed integer instructions.
-system.cpu.commit.COM:loads 148952608 #
Number of loads committed
+system.cpu.commit.COM:int_insts 533522691 #
Number of committed integer instructions.
+system.cpu.commit.COM:loads 148952607 #
Number of loads committed
system.cpu.commit.COM:membars 1328 #
Number of memory barriers committed
-system.cpu.commit.COM:refs 219173635 #
Number of memory references committed
+system.cpu.commit.COM:refs 219173633 #
Number of memory references committed
system.cpu.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 3894768 #
The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 602359921 #
The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 6311 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 86755718 #
The number of squashed insts skipped by commit
-system.cpu.committedInsts 602359870 #
Number of Instructions Simulated
-system.cpu.committedInsts_total 602359870 #
Number of Instructions Simulated
-system.cpu.cpi 0.652556 #
CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.652556 #
CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 1359 #
number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 10642.857143
# average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_hits 1345 #
number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 149000
# number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate 0.010302 #
miss rate for LoadLockedReq accesses
+system.cpu.commit.branchMispredicts 3891220 #
The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 602359916 #
The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 6310 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 86859726 #
The number of squashed insts skipped by commit
+system.cpu.committedInsts 602359865 #
Number of Instructions Simulated
+system.cpu.committedInsts_total 602359865 #
Number of Instructions Simulated
+system.cpu.cpi 0.652478 #
CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.652478 #
CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 1356 #
number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 10607.142857
# average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_hits 1342 #
number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 148500
# number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate 0.010324 #
miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_misses 14 #
number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_mshr_hits 14 #
number of LoadLockedReq MSHR hits
-system.cpu.dcache.ReadReq_accesses 139417902 #
number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13041.209813
# average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7899.689585
# average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 139176030 #
number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3154303500 #
number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.001735 #
miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 241872 #
number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 46005 #
number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1547288500
# number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001405 #
mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 195867 #
number of ReadReq MSHR misses
-system.cpu.dcache.StoreCondReq_accesses 1341 #
number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits 1341 #
number of StoreCondReq hits
+system.cpu.dcache.ReadReq_accesses 139395234 #
number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13041.881358
# average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7904.223289
# average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 139153026 #
number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3158848000 #
number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.001738 #
miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 242208 #
number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 46247 #
number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1548919500
# number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001406 #
mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 195961 #
number of ReadReq MSHR misses
+system.cpu.dcache.StoreCondReq_accesses 1340 #
number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits 1340 #
number of StoreCondReq hits
system.cpu.dcache.WriteReq_accesses 69417531 #
number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17903.398328
# average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10349.195917
# average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 67926226 #
number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 26699427444 #
number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.021483 #
miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1491305 #
number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1243450 #
number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2565099954
# number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.003570 #
mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 247855 #
number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4339.606397
# average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 17910.212192
# average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10351.034278
# average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 67926304 #
number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 26708191996 #
number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.021482 #
miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1491227 #
number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1243368 #
number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2565597005
# number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 #
mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 247859 #
number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 4376.771337
# average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value
# average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 466.744813 #
Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 2251 #
number of cycles access was blocked
+system.cpu.dcache.avg_refs 466.592209 #
Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 2191 #
number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 #
number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 9768454
# number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 9589506
# number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0
# number of cycles access was blocked
system.cpu.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu.dcache.demand_accesses 208835433 #
number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 17224.859864 #
average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9267.939056
# average overall mshr miss latency
-system.cpu.dcache.demand_hits 207102256 #
number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 29853730944 #
number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.008299 #
miss rate for demand accesses
-system.cpu.dcache.demand_misses 1733177 #
number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1289455 #
number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4112388454
# number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 208812765 #
number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 17229.974009 #
average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9270.687452
# average overall mshr miss latency
+system.cpu.dcache.demand_hits 207079330 #
number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29867039996 #
number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.008301 #
miss rate for demand accesses
+system.cpu.dcache.demand_misses 1733435 #
number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1289615 #
number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4114516505
# number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002125 #
mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 443722 #
number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 443820 #
number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 #
number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999720 #
Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.852027 #
Average occupied blocks per context
-system.cpu.dcache.overall_accesses 208835433 #
number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 17224.859864
# average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9267.939056
# average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999719 #
Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.849519 #
Average occupied blocks per context
+system.cpu.dcache.overall_accesses 208812765 #
number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 17229.974009
# average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9270.687452
# average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value
# average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 207102256 #
number of overall hits
-system.cpu.dcache.overall_miss_latency 29853730944 #
number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.008299 #
miss rate for overall accesses
-system.cpu.dcache.overall_misses 1733177 #
number of overall misses
-system.cpu.dcache.overall_mshr_hits 1289455 #
number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4112388454
# number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 207079330 #
number of overall hits
+system.cpu.dcache.overall_miss_latency 29867039996 #
number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.008301 #
miss rate for overall accesses
+system.cpu.dcache.overall_misses 1733435 #
number of overall misses
+system.cpu.dcache.overall_mshr_hits 1289615 #
number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4114516505
# number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002125 #
mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 443722 #
number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 443820 #
number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0
# number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 439626 #
number of replacements
-system.cpu.dcache.sampled_refs 443722 #
Sample count of references to valid blocks.
+system.cpu.dcache.replacements 439722 #
number of replacements
+system.cpu.dcache.sampled_refs 443818 #
Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 #
number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.852027 #
Cycle average of tags in use
-system.cpu.dcache.total_refs 207104942 #
Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 89209000 #
Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 394231 #
number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 63976815 #
Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 1279 #
Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 5983185 #
Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 722294449 #
Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 163843845 #
Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 138493802 #
Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 12857426 #
Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 4707 #
Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 12987991 #
Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse 4094.849519 #
Cycle average of tags in use
+system.cpu.dcache.total_refs 207082021 #
Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 89315000 #
Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 394264 #
number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 64227537 #
Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 1274 #
Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 5983982 #
Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 722350979 #
Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 163737957 #
Number of cycles decode is idle
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