changeset 5275c2fbe957 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=5275c2fbe957
description:
Sim: Fix Simulation.py to allow more than 1 core for standard switching.
This patch moves the assignment of testsys.switch_cpus,
testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they
are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.
diffstat:
configs/common/Simulation.py | 18 +++++++++---------
1 files changed, 9 insertions(+), 9 deletions(-)
diffs (35 lines):
diff -r 20362a3a1540 -r 5275c2fbe957 configs/common/Simulation.py
--- a/configs/common/Simulation.py Mon Apr 04 11:42:31 2011 -0500
+++ b/configs/common/Simulation.py Mon Apr 04 11:42:31 2011 -0500
@@ -123,6 +123,11 @@
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
if options.standard_switch:
+ if not options.caches:
+ # O3 CPU must have a cache to work.
+ print "O3 CPU must be used with caches"
+ sys.exit(1)
+
switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
for i in xrange(np)]
switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
@@ -161,15 +166,10 @@
if options.max_inst:
switch_cpus_1[i].max_insts_any_thread = options.max_inst
- if not options.caches:
- # O3 CPU must have a cache to work.
- print "O3 CPU must be used with caches"
- sys.exit(1)
-
- testsys.switch_cpus = switch_cpus
- testsys.switch_cpus_1 = switch_cpus_1
- switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
- switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in
xrange(np)]
+ testsys.switch_cpus = switch_cpus
+ testsys.switch_cpus_1 = switch_cpus_1
+ switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in
xrange(np)]
+ switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in
xrange(np)]
# set the checkpoint in the cpu before m5.instantiate is called
if options.take_checkpoints != None and \
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
