> > I realize the documentation is still under way for gem5, but I was > > wondering if there are any plans to document how users should be > > interpreting the Ruby stats file? (Particularly, the miss latency > > histograms)
Not all protocols support the miss latency histograms. Specifically, I believe only the hammer protocol supports all of them. Do you have any particular questions about them? > > > > Did people come to the conclusion that it is a good idea to have a > > separate files for ruby stats v. m5 stats (if so, sorry for the extra > > question)? > > I'm not sure we have a final decision on that, but Derek is the one currently looking into it. > > Additionally, is there an update on any plans to add descriptions and > > do stats accounting for the various cache memories? To my surprise, I > > always get this output for any CacheMemory in Ruby: > > "Cache Stats: system.l1_cntrl0.L1IcacheMemory > > system.l1_cntrl0.L1IcacheMemory_total_misses: 0 > > system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 > > system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 > > system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 > > system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0" > > > > For now it looks like I'll have to derive some pseudo-information from > > the Cache event and transition counts OR go in and try to hack in some > > of these stats myself. But ideally, I would say one aggregated stat > > file where I could grep out about cpu and detailed memory stats (i.e. > > what about mshr miss/hit counts?) would be awesome. > > > > If all this stuff is there, please excuse my ignorance, but if not, > > would someone be so kind to provide a brief update of what's going on > with this? The stats you mentioned are supported by some protocols but not others. Basically those protocols that do support them, include special actions that increment these stats. In my opinion, it is really hard to make these stats protocol agnostic, but you're welcome to propose a methodology that does. Brad _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
