I don't have anything definitive about Ruby vs. M5 stats, but until there is anything definitive, I use both depending on what I'm trying to do.
I've added my own M5 stats to the Ruby Caches because I know those stats much better, but I've also looked at existing Ruby stats when I know they answer what I want. Basically, the miss latency histograms are histograms because of network issues, since everything is sent around Ruby in messages and there may be contention, there is no fixed latency for when, say, a request message gets from a CPU to memory and back. So this histogram is basically telling you how many requests took X cycles, Y cycle, Z cycles, but it should be fairly apparent that most are clustered around a particular value. So, the L1 miss latency tells you the distribution of times it took for hits in the L1, and the average is the average L1 hit time. I don't believe there are any MSHR stats in Ruby. Finally, what Brad is saying about the protocol agnosticness is that to make the Ruby stats increment, you have to make specific calls *from* the protocol definition itself, it's not contained in the caches. So, if you, say, forget to have it miss when there is a miss in the protocol, you'll be missing some misses (haha) in your stats, and if you write a new protocol where you never do any of these callouts, then you'll have zeros for all your stats. Lisa On Tue, Apr 5, 2011 at 9:54 AM, Korey Sewell <[email protected]> wrote: > Hi All, > I realize the documentation is still under way for gem5, but I was > wondering > if there are any plans to document how users should be interpreting the > Ruby stats file? (Particularly, the miss latency histograms) > > Did people come to the conclusion that it is a good idea to have a separate > files for ruby stats v. m5 stats (if so, sorry for the extra question)? > > Additionally, is there an update on any plans to add descriptions and do > stats accounting for the various cache memories? To my surprise, I always > get this output for any CacheMemory in Ruby: > "Cache Stats: system.l1_cntrl0.L1IcacheMemory > system.l1_cntrl0.L1IcacheMemory_total_misses: 0 > system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0 > system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 > system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 > system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0" > > For now it looks like I'll have to derive some pseudo-information from the > Cache event and transition counts OR go in and try to hack in some of these > stats myself. But ideally, I would say one aggregated stat file where I > could grep out about cpu and detailed memory stats (i.e. what about mshr > miss/hit counts?) would be awesome. > > If all this stuff is there, please excuse my ignorance, but if not, would > someone be so kind to provide a brief update of what's going on with this? > > Thanks! > > -- > - Korey > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
