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(Updated 2011-06-01 18:59:39.117342) Review request for Default. Summary ------- Ruby: Add support for functional accesses This patch is meant for implementing functional access support in Ruby. There is one significant change from the previous version of the patch. In the previous version, during functional writes, only the cache memories were being checked. During testing I realized that some of the cache lines could reside in the TBEs. So, now the check is being done at the controller level. The controller has to provide a function called getAccessPermission() for functional accesses to be successful. The default implementation of the function returns "busy" which means that the functional access cannot proceed further. The patch has been tested only for 10000 loads and processor count from 1 to 16. Diffs ----- configs/example/ruby_mem_test.py 681497e0356b configs/ruby/MESI_CMP_directory.py 681497e0356b configs/ruby/MI_example.py 681497e0356b configs/ruby/MOESI_CMP_directory.py 681497e0356b configs/ruby/MOESI_CMP_token.py 681497e0356b configs/ruby/MOESI_hammer.py 681497e0356b configs/ruby/Ruby.py 681497e0356b src/cpu/testers/memtest/memtest.hh 681497e0356b src/cpu/testers/memtest/memtest.cc 681497e0356b src/mem/packet.hh 681497e0356b src/mem/packet.cc 681497e0356b src/mem/protocol/MESI_CMP_directory-L1cache.sm 681497e0356b src/mem/protocol/MESI_CMP_directory-L2cache.sm 681497e0356b src/mem/protocol/MESI_CMP_directory-dir.sm 681497e0356b src/mem/protocol/MI_example-cache.sm 681497e0356b src/mem/protocol/MI_example-dir.sm 681497e0356b src/mem/protocol/MOESI_CMP_directory-L1cache.sm 681497e0356b src/mem/protocol/MOESI_CMP_directory-L2cache.sm 681497e0356b src/mem/protocol/MOESI_CMP_directory-dir.sm 681497e0356b src/mem/protocol/MOESI_CMP_token-L1cache.sm 681497e0356b src/mem/protocol/MOESI_CMP_token-L2cache.sm 681497e0356b src/mem/protocol/MOESI_CMP_token-dir.sm 681497e0356b src/mem/protocol/MOESI_hammer-cache.sm 681497e0356b src/mem/protocol/MOESI_hammer-dir.sm 681497e0356b src/mem/ruby/network/Network.cc 681497e0356b src/mem/ruby/network/Network.py 681497e0356b src/mem/ruby/profiler/Profiler.cc 681497e0356b src/mem/ruby/profiler/Profiler.py 681497e0356b src/mem/ruby/recorder/Tracer.cc 681497e0356b src/mem/ruby/recorder/Tracer.py 681497e0356b src/mem/ruby/slicc_interface/AbstractController.hh 681497e0356b src/mem/ruby/slicc_interface/Controller.py 681497e0356b src/mem/ruby/slicc_interface/SConscript 681497e0356b src/mem/ruby/system/AbstractMemory.hh PRE-CREATION src/mem/ruby/system/AbstractMemory.cc PRE-CREATION src/mem/ruby/system/AbstractMemory.py PRE-CREATION src/mem/ruby/system/Cache.py 681497e0356b src/mem/ruby/system/CacheMemory.hh 681497e0356b src/mem/ruby/system/CacheMemory.cc 681497e0356b src/mem/ruby/system/DirectoryMemory.hh 681497e0356b src/mem/ruby/system/DirectoryMemory.cc 681497e0356b src/mem/ruby/system/DirectoryMemory.py 681497e0356b src/mem/ruby/system/RubyPort.hh 681497e0356b src/mem/ruby/system/RubyPort.cc 681497e0356b src/mem/ruby/system/RubySystem.py 681497e0356b src/mem/ruby/system/SConscript 681497e0356b src/mem/ruby/system/Sequencer.py 681497e0356b src/mem/ruby/system/System.hh 681497e0356b src/mem/ruby/system/System.cc 681497e0356b src/mem/slicc/ast/MemberExprAST.py 681497e0356b src/mem/slicc/symbols/Func.py 681497e0356b src/mem/slicc/symbols/StateMachine.py 681497e0356b Diff: http://reviews.m5sim.org/r/611/diff Testing (updated) ------- Thanks, Nilay _______________________________________________ gem5-dev mailing list gem5-dev@m5sim.org http://m5sim.org/mailman/listinfo/gem5-dev
