hi, Currently for configuring the cache delay we have to use *time* metric (say 2ns). Is it possible to convert it to macine cycles? In some papers this delay is represented by 1cycles.
Assume core frequency is 1.0 GHz. So one tick takes 1ns. If we want to logically set L1 latency to 1 cycles, how many ticks should we consider? -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
