I assume that macine cycle is 1ns since the cpu frequency is 1.0 GHz. So a 2 cycle latency is the same as 2ns.
Need a confirmation. P.S: I think I read a post from Steve on the archive that calculates this by a formula. But I can not find that. On 1/24/12, Paul Rosenfeld <dramnin...@gmail.com> wrote: > Erm, sorry I completely misread your question. > > On Tue, Jan 24, 2012 at 2:57 PM, Paul Rosenfeld <dramnin...@gmail.com>wrote: > >> The other day I stumbled upon this code in tport.cc: >> >> assert(when > curTick()); >> assert(when < curTick() + SimClock::Int::ms); >> >> There's also a field called: >> >> SimClock::Int::ns; >> >> So perhaps this is what you're looking for. >> >> >> On Mon, Jan 23, 2012 at 11:21 AM, Mahmood Naderan >> <mahmood...@gmail.com>wrote: >> >>> hi, >>> Currently for configuring the cache delay we have to use *time* metric >>> (say 2ns). >>> Is it possible to convert it to macine cycles? In some papers this >>> delay is represented by 1cycles. >>> >>> Assume core frequency is 1.0 GHz. So one tick takes 1ns. If we want to >>> logically set L1 latency to 1 cycles, how many ticks should we >>> consider? >>> >>> -- >>> // Naderan *Mahmood; >>> _______________________________________________ >>> gem5-users mailing list >>> gem5-users@gem5.org >>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users >>> >> >> > -- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
