No. If a cache has two ports, then 2 simultaneous accesses to this cache can be serviced. I meant this
On 1/26/12, Jack Harvard <jack.harv...@gmail.com> wrote: > Why you would want to change the number of cache ports? Would expect > one port on the CPU side and one port on the MEM side. See > src/mem/cache/base.hh > > Jack Harvard > > > > On Wed, Jan 25, 2012 at 6:51 AM, Mahmood Naderan <mahmood...@gmail.com> > wrote: >> Hi, >> Is it possible to change the number of cache ports? I can not find it in >> BaseCache.py >> >> -- >> // Naderan *Mahmood; >> >> _______________________________________________ >> gem5-users mailing list >> gem5-users@gem5.org >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > -- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
