hmm... what is this cachePorts = Param.Unsigned(200, "Cache Ports")
http://grok.gem5.org/source/xref/m5/src/cpu/o3/O3CPU.py#55 On 1/26/12, Mahmood Naderan <mahmood...@gmail.com> wrote: > so that mean only one port is available from cpu to cache and one port > is available from cache to mem. > Also that mean, if two requests are arrived to cache port (two request > have one source, either cpu or mem), they are serviced sequentially. > Is that right? > > On 1/26/12, William Wang <william.w...@arm.com> wrote: >> The ports are created in the constructor Cache<TagStore>::Cache() >> >> http://www.m5sim.org/docs/cache__impl_8hh_source.html#l00066 >> >> >> >> Defined in base.hh >> >> http://www.m5sim.org/docs/mem_2cache_2base_8hh_source.html#l00148 >> >> >> From: gem5-users-boun...@gem5.org [mailto:gem5-users-boun...@gem5.org] On >> Behalf Of Mahmood Naderan >> Sent: 25 January 2012 06:51 >> To: gem5 users mailing list >> Subject: [gem5-users] number of cache ports >> >> Hi, >> Is it possible to change the number of cache ports? I can not find it in >> BaseCache.py >> >> -- >> // Naderan *Mahmood; >> >> -- IMPORTANT NOTICE: The contents of this email and any attachments are >> confidential and may also be privileged. If you are not the intended >> recipient, please notify the sender immediately and do not disclose the >> contents to any other person, use it for any purpose, or store or copy >> the >> information in any medium. Thank you. > > > -- > -- > // Naderan *Mahmood; > -- -- // Naderan *Mahmood; _______________________________________________ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
