Hello,
For a default memory configuration using SimpleMemory in SE mode,
config.ini is showing a latency of 30000. Is this latency in cycles
(same question for cache latency values)? In addition, a professor has
told me that typical DRAM latency is more like 300 cycles; can someone
explain the factor of 100 difference?
Finally, what's the easiest way to change the memory latency for our
simulation?
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:536870911
zero=false
port=system.membus.master[0]
Thanks,
David G.
--
David Gloe
Masters Student, Computer Science
University of Minnesota
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