A latency of 30000 means 30000 ps, or 30 ns. To change it, you may edit src/mem/SimpleMemory.py or may define a new command option using the configs/common/Options.py file.
Thanks, Amin On Tue, May 7, 2013 at 12:21 PM, David Gloe <gloex...@umn.edu> wrote: > Hello, > > For a default memory configuration using SimpleMemory in SE mode, > config.ini is showing a latency of 30000. Is this latency in cycles (same > question for cache latency values)? In addition, a professor has told me > that typical DRAM latency is more like 300 cycles; can someone explain the > factor of 100 difference? > > Finally, what's the easiest way to change the memory latency for our > simulation? > > [system.physmem] > type=SimpleMemory > bandwidth=73.000000 > clock=1000 > conf_table_reported=false > in_addr_map=true > latency=30000 > latency_var=0 > null=false > range=0:536870911 > zero=false > port=system.membus.master[0] > > Thanks, > David G. > > -- > David Gloe > Masters Student, Computer Science > University of Minnesota > > ______________________________**_________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/**mailman/listinfo/gem5-users<http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users> >
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