Thanks a lot for your prompt reply.

I'm currently having L1 shared between two cores. The dcache_port on each
CPU is connected to a bus which is in turn connected to L1 D Cache.

My understanding was that there can't be memory accesses from both the
CPU's in the same cycle (even if it belonged to two different cache lines).

However, if the L1 D cache has one dedicated port for each CPU, then the
accesses can be parallelized.

Thanks a lot!
V Vanchinathan


On Mon, Jul 21, 2014 at 8:38 PM, Andreas Hansson <andreas.hans...@arm.com>
wrote:

>  Hi,
>
>  It is not obvious what you are trying to achieve here. Could you shed
> some more details on what you are after? Are you looking for more bandwidth
> to the L1 (if is already infinite)? Are you looking to have more
> outstanding transactions (it is already a parameter)? Are you looking to
> share the L1 between to cores (if so use a bus/crossbar)?
>
>  Andreas
>
>
>   From: Vanchinathan Venkataramani via gem5-users <gem5-users@gem5.org>
> Reply-To: Vanchinathan Venkataramani <dcsv...@gmail.com>, gem5 users
> mailing list <gem5-users@gem5.org>
> Date: Monday, 21 July 2014 12:16
> To: gem5 users mailing list <gem5-users@gem5.org>
> Subject: [gem5-users] Having multi-ported L1 Cache
>
>  I would like to know if it is possible to connect the dcache_port of a
> CPU to separate ports on L1 Cache in classic memory model.
>
> Currently L1 cache has a single cpu_side port. I wanted to know if the
> functionality will be correct if I change this to a vector instead and
> connect each of the CPU dcache_port to this.
>
>  Thanks
> V Vanchinathan
>
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