Hello Everybody, I am using DDR3_1600_x64. I am trying to understand the memory controller design and have few doubts about it.
1) Do the memory controller has a separate Bank request buffer (read and write buffer) for each bank or just a global queue? 2) Is there a scheduler per bank which arbitrates between different queue requests parallel with other bank schedulers? 3) Is there DRAM bus scheduler that arbitrates between different bank requests? Thanks, Prathap
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