Hi
I want to know the requester id of the processor who requests the cache
block. I want this specifically at the time of allocation in L2, i.e. when
L1 of the specific processor request it for first time. I am using MESI Two
Level.
In the file MESI_Two_Level-L2cache.sm I can see that
qq_allocateL2CacheBlock action is called which inturns
call L2cache.allocate. In the CacheMemory.cc I can see the function
allocate, but in the RubySlicc_Types.sm I am unable to see allocate
function declaration. I can see for other like deallocate, setMRU but not
for allocate. There is allocateVoid, which in CacheMemory.hh calls allocate
as follows: (There is no allocate in CacheMemory.hh)
// find an unused entry and sets the tag appropriate for the address
AbstractCacheEntry* allocate(const Address& address,
AbstractCacheEntry* new_entry, const MachineID& machineID);
void allocateVoid(const Address& address, AbstractCacheEntry*
new_entry, const MachineID& machineID)
{
allocate(address, new_entry, machineID);
}
NOTE: I have added MachineID for getting requestor ID.
So I have 2 questions:
- How is this allocateVoid related to allocate as in how does action
qq_allocateL2CacheBlock calls allocate and where does allocate Void comes
in picture?
- And when I compile with the changes I get following error:
Exception: MESI_Two_Level-L2cache.sm:662: Error: Invalid method call: Type
'CacheMemory' does not have a method allocate,
'allocate_Address_L2Cache_Entry_MachineID' nor
'allocate_Address_AbstractCacheEntry_MachineID':
Changes are as follows:
****************************************************************
File: /gem5-stable/src/mem/protocol/RubySlicc_Types.sm
****************************************************************
structure (CacheMemory, external = "yes") {
bool cacheAvail(Address);
Address cacheProbe(Address);
AbstractCacheEntry allocate(Address, AbstractCacheEntry);
void allocateVoid(Address, AbstractCacheEntry, MachineID);
//Change
void deallocate(Address);
AbstractCacheEntry lookup(Address);
bool isTagPresent(Address);
void setMRU(Address);
void recordRequestType(CacheRequestType);
bool checkResourceAvailable(CacheResourceType, Address);
Scalar demand_misses;
Scalar demand_hits;
}
****************************************************************
File: /gem5-stable/src/mem/protocol/MESI_Two_Level-L2cache.sm
****************************************************************
action(qq_allocateL2CacheBlock, "\q", desc="Set L2 cache tag equal to tag
of block B.") {
if (is_invalid(cache_entry)) {
peek(L1RequestL2Network_in, RequestMsg) {
//Change
set_cache_entry(L2cache.allocate(address, new Entry,
in_msg.Requestor)); } //Change
}
}
****************************************************************
File: /gem5-stable/src/mem/ruby/structures/CacheMemory.hh
****************************************************************
// find an unused entry and sets the tag appropriate for the address
AbstractCacheEntry* allocate(const Address& address,
AbstractCacheEntry* new_entry, const MachineID& machineID); //Change
void allocateVoid(const Address& address, AbstractCacheEntry*
new_entry, const MachineID& machineID) //Change
{
allocate(address, new_entry, machineID);
//Change
}
****************************************************************
File: /gem5-stable/src/mem/ruby/structures/CacheMemory.cc
****************************************************************
AbstractCacheEntry*
CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry,
const MachineID& machineID) //Change
{
assert(address == line_address(address));
assert(!isTagPresent(address));
assert(cacheAvail(address));
DPRINTF(RubyCache, "address: %s\n", address);
int processor_requestor = machineID.getNum();
//Change
DPRINTF(RubyCache, "Davesh: loc: %d\n", processor_requestor);
//Change
// Find the first open slot
int64 cacheSet = addressToCacheSet(address);
std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
for (int i = 0; i < m_cache_assoc; i++) {
if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent)
{
set[i] = entry; // Init entry
set[i]->m_Address = address;
set[i]->m_Permission = AccessPermission_Invalid;
DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
address);
set[i]->m_locked = -1;
m_tag_index[address] = i;
m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
return entry;
}
}
panic("Allocate didn't find an available entry");
}
--
Have a great day!
Thanks and Warm Regards
Davesh Shingari
Master's in Computer Engineering [EE]
Arizona State University
[email protected]
ᐧ
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