Hello All, I am simulating an ARM O3 multi-core system with private L1 cache and a Shared L2 cache. I am investigating the MSHR contention in the L2 cache. If cache has no free MSHRs, this Marks the access path of the cache as blocked and also sets the blocked flag in the slave interface.This means there won't be any further access to the L2 cache. Instead of blocking the L2 cache altogether, i would like to place a MSHR reservation to a selected core. So that requests from only selected core are blocked based on its respective MSHR utilization.
I am not sure if this is feasible. Do L2 Bus has an arbitrator which can be modified to do this? Thanks, Prathap
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